EagleCAD schenatics archive download
Imported in Kicad, exported as SVG images on this page:
Logic concept
Clock Generator
Reset
RS0
A0
A9
CS1 Latch
RW
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PB7 driver/buffer
a href="http://retro.hansotten.nl/wp-content/uploads/2021/11/6530-004_dissect_9-6530-004_dissect_9.svg">
PB6 driver/buffer
PB0 driver/buffer
PLA
Some logic
I/O control
I/O logic, Bit 7
Timer control
Predivider
Timer (don countyer)
RAM row buffer/driver
ROM
See also:
EMUF M50734
In the MC Magazine 11 1991 a special EMUF is published.
It is based upon the 6502 compatible Mitsubishi M50734 CPU. T...
KGN COMAL
COMAL is an interpreted structured language. A version for the KIM-1, Junior and DIS65 is available, distributed by the ...
6530 hardware emulator in FPGA in 40 pin DIP
Imagine a true 6530-002 and 6530-003 replacement , the RRIOTs of the KIM-1
Now with modern FPGAs you van do that...
PAL-2
4 february 2025 2025 I have built the PAl-2 kit, now designing and building a I/O card.
This information is based upon ...