EagleCAD schenatics archive download
Imported in Kicad, exported as SVG images on this page:
Logic concept
Clock Generator
Reset
RS0
A0
A9
CS1 Latch
RW
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PB7 driver/buffer
a href="http://retro.hansotten.nl/wp-content/uploads/2021/11/6530-004_dissect_9-6530-004_dissect_9.svg">
PB6 driver/buffer
PB0 driver/buffer
PLA
Some logic
I/O control
I/O logic, Bit 7
Timer control
Predivider
Timer (don countyer)
RAM row buffer/driver
ROM
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