EagleCAD schenatics archive download
Imported in Kicad, exported as SVG images on this page:
Logic concept
Clock Generator
Reset
RS0
A0
A9
CS1 Latch
RW
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PB7 driver/buffer
a href="http://retro.hansotten.nl/wp-content/uploads/2021/11/6530-004_dissect_9-6530-004_dissect_9.svg">
PB6 driver/buffer
PB0 driver/buffer
PLA
Some logic
I/O control
I/O logic, Bit 7
Timer control
Predivider
Timer (don countyer)
RAM row buffer/driver
ROM
See also:
Replica 1 TE PAL version
User ExPLIT on the German forum Verein zum Erhalt klassischer Computer e.V.
has build an Apple 1 Replica 1 TE from th...
Jolt with 4K and power supply
With thanks to Jonathan Chapman of Glitchworks who found a Jolt system, here images of a Jolt with 4K memory, an experim...
TERC KIM-1 Interface set
A recent acquisition, the TERC (Technical Education Research Centers) KIM-1 Interface set. An educational tool to work w...
6502 tester NMOS CMOS 1-8MHz
The 6502 W65C02 6502C CPU tester NMOS / CMOS 1-8MHz is a CPU tester for 40 pin 6502/65C02 and WD65C02 and Sally.
The...