Here you can find the product announcements from MTU. Starting with KIM-1 products like the K-1008 Visable memory in 1978 to the large product range for KIM-1, SYM-1, AIM 65 and PET CBM Commodore and Apple. Not just product descriptions, but also in depth information on the products. All newly scanned and corrected in July 2025.
MTU Product Descriptions 1978
KIM-1 products like 16K RAM board K-1016, K-1008 Visable Memory, K-1000 PSU, K-1005 card file
All MTU expansions, be it card cages with motherboards, memory, video, floppy disk cards use the MTU/KIM-1 bus.
PRINCIPLES OF OPERATION
Actually there is not much theory behind the operation of 5 edge connectors, 44 parallel wires and a terminal strip. What can be discussed however is the philosophy behind the K-1005 series of card files and its associated KIM/MTU bus. The Commodore KIM-1 single-board microcomputer was first released in 1976 and is the grandparent of the Synertek SYM-1 (formerly the VIM-1) and Rockwell AIM-65 micro-computers. Even the Commodore PET shows some KIM-1 influence. These processors cover the vast majority of 6502 based systems in use today and are the ones supported most vigorously by MTU.
WHY THE KIM BUS?
The original KIM-1 was a well thought-out product that hit on just the right tradeoff between system resources and selling price. Some amazing things have been done in its 1K memory such as the first generally available microcomputer chess program, the first 4 voice all software music synthesis program, Tiny BASIC, and others. However at some point every system needs to be expanded and the KIM and its relatives are no exception.
Commodore’s answer for expansion was the KIM-4 expansion bus and KIM-3 memory board. Independent manufacturers introduced similar expansion bus boards while others offered expansion systems based on the Altair (S-100) bus. The S-100 bus adapters were more successful because there was a multitude of expansion boards from which to choose. One pitfall in the S-100 technique is that not all S-100 boards would work properly with 6502 timing signals. The main common fault with the mechanical implementation of these products is their open-air construction which offers little protection for the boards and eliminates portability.
MTU’s first KIM expansion product was the K-1008 Visible Memory. The idea behind the VM was to have a board at the price of a plain 8K memory which would also show a high resolution video image. The goal was to capture both the KIM add-on memory and video display market with a single product. In deciding how it should connect to the KIM we had several factors to consider. First, it seemed like a poor idea to produce a board to plug into a bus (KIM-4) that few potential customers had. On the other hand an S-100 environment would have prohibited our use of 6502 timing properties to produce a totally transparent memory and snow-free display. In the final analysis it seemed desirable to produce a board that re-quired no motherboard or bus at all to connect and thus be available at a much lower “installed” price. The logical conclusion was simply direct parallel connection to the KIM-1 Expansion connector!
The KIM BUS, which is the signals on the KIM’s expansion edge connector, for the most part uses the actual signals from the 6502 microcomputer itself. Further-more the SYM-1 and AIM-65 Expansion connector busses are for practical purposes identical to the KIM-1 bus. The combined number of these processors sold makes the KIM bus one of the most widely used and to date has suffered less from compatibility problems than any other multi-vendor personal computer bus structure.
We have since designed and manufactured 4 additional expansion boards that may be used alone in the same manner. In order to support those customers who wish to use several of our expansion boards, we designed the K-1005 motherboard/card file which is simply a convenient method of connecting several boards to the processor’s expansion connector along with the necessary mechanical support provisions.
PLAIN OR BUFFERED?
Probably the most frequently asked question regarding the K-1005 is “Why is the bus not buffered?”. The basic answer is that buffering is not needed for only 4 expansion boards. The next question then is “Why not buffer it anyway to reduce microprocessor loading, provide noise immunity, and improve signal rise times?”. The answer to that is somewhat more technical but in a nutshell buffering has some of its own problems and it is not necessarily true that it improves system operating margins when the unbuffered equivalent does not violate any loading rules.
The KIM bus address and data lines are simply the corresponding microprocessor busses brought out to edge fingers. The various control signals (PHASE 2 and READ/WRITE) are indeed buffered by TTL gates on the processor board. The unbuffered address and data lines are rated by the microprocessor manufacturer to drive 1.7MA of DC loading and 170pF of capacitance. This figures out to 5 low power Schottky TTL (74LS series) inputs (MOS inputs such as to memory IC’s have no DC load) and about 35 circuit connections at 5pF per connection. The processor board itself uses one low power Schottky load and about a dozen connections (more connections on SYM and AIM processors). This leaves 4 low power Schottky inputs and over a dozen connections for the external bus which is adequate for implementing a 4 slot expansion bus. This is the main reason the K-1005 has 5 slots including processor.
Probably the most misunderstood aspect of buffering is noise generation and immunity. In theory low impedance TTL or TRI-STATE bus drivers should be able to “short out” noise spikes much better than high impedance MOS outputs can. This may be true, but in practice TTL or high power TRI-STATE bus buffers generate so much noise when they switch that almost nothing can absorb it. The problem is most acute in large systems (such as minicomputers and S-100 computers) where as many as 24 buffers with 100MA surge capability and nanosecond rise times can switch simultaneously thus placing a 2.5 amp reaction current surge through the GROUND leads of the bus. It is not unusual to see over a half volt differential in GROUND voltages between driving and receiving boards in such a system. In practice such spikes interfere with the bus CONTROL signals which results in unpredictable occurrances such as spurious writing into memory or falsely triggering an I/O device. Seldom are address and data bus signals themselves read wrong even though they cause the noise because they are ignored while changing (under the direction of control signals). indicate that all changing must have ended and the data be stable at it’s “0” or “1” state. It is instructive to note that minicomputer busses (such as the DEC UNIBUS and the NOVA bus) specify the use of filter and delay circuits on control signal lines received by interface boards. In addition, these systems typically have multilayer backplanes with ground planes to shield and shunt noise.
With unbuffered MOS and low power (8 MA) 74LS TTL bus drivers, such noise is almost completely absent. The author has had considerable experience in designing and troubleshooting bus systems and the unbuffered KIM bus is among the quietest encountered. With respect to rise time, 8MA is sufficient to swing 170PF (which is actually a rather heavy bus load) from logic zero to one or vice-versa within 65NS which is quite adequate for 1MHz 6502 operation. Note that this time has already been factored into the 6502 timing specifications. Remember also that bus buffers do have their own propagation delay times.
KIM BUS -VS- KIM/MTU BUS
As the reader may have guessed, the bus implemented on the K—1005 motherboard is not strictly a KIM—I bus. If it were, all 44 lines would be run strictly parallel up and down the board. The MTU modification amounts to assigning the top slot to the CPU (except for the PET version where all slots are equivalent) and not connecting some of the pins to the expansion bus below. This then frees up several lines on the expansion bus for other functions that do not relate to the CPU or computer bus operation,
Two of the pins are used to provide unregulated +8 and +16 volt power to the expansion boards, which the CPU does not use, Two more pins are used for the DECODE ENABLE and VECTOR FETCH signals that KIM-I systems require (unnecessary for AIM—65 and SYM—1). An additional three pins are used (in PET systems only) to carry separated Vertical, Horizontal and Video signals to a separate sync video monitor. Finally there is one spare set aside for future use. The following page lists the signals of each processor and those of the KIM/MTU bus used on the K-1005.
In providing these expansion bus signals, some signals from the CPU are not available on the bus, The most significant of these are READY and PHASE 1, PHASE 1 is equivalent to PHASE 2 the inverse of PHASE 2 which is available on the bus, Modern memories are fast enough so that wait states are not needed, thus the •READY signal. is of no use, Besides, the 6502 will not wait during a write cycle anyway.
MTU documents, 1979-1983, collected from several sources.
The early ones are for the MTU products aimed at the KIM-1, SYM-1 and AIM 65.
The later ones for the MTU-130/140 system.
– own scans of original MTU documents
– scans by Jack Rubin
– scans by Dave Plummer
– scans by David Williams
– scans by anonymous persons found on the internet
– help from Eduardo Casino
As of July 2025 this is a work in progress. The list is complete, not all scans are made or corrected.
List of not yet scanned/double/check already scanned/ originals
K-1002-3 Source PET Music Software May 1979
K-1002-1L 8 bit Digital Music Software Simplified Interpreter, Notran Interpreter Compiler sources Jan 1979
K-1002 8 bit audio DA converter hardware manual July 1979
Done: K-1005 Card file and 5 slot motherboard KIM/MTU bus Nov 1979
K-1008 Visible Memory revised september 1979
K-1008-1L Graphic/Text subroutines Jan 1979
K-1008-2L Patches to Microsoft Basic Feb 1979
K-1008-3 Level 1 Graphic Software for all Commodore PET-2001 July 1979
K-1008-5C Visible Memory Demonstration, AIM 65 Basic, Subroutine package Jan 1980
K-1008-6 Integrated Visible Memory for PET and CBM April 1980
K-1009-1C AIM-65 Printer Enhancement Package April 1980
K-1012 System board PROM I/O Comm Programmer May 1979
K-1012 PROM/IO board Revised Jan 1980
K-1013 Double Density Disk Controller for KIM/MTU Bus May 1980
K-1016 16K Byte Memory Jan 1979
K-1016 16K Byte Memory revised September 1979
K-1020 Prototyping board April 1979
K-1002-6C PET Instrument Synthesis Software Package October 1980
K-1002-7C KIM-1 Instrument Synthesis Software Package October 1980
K-1002-8C AIM 65 Instrument Synthesis Software Package October 1980
Apex065 Operating System User’s manual AIM Preliminary July 1980
MTU CODOS Operating System User’s manual Release 1.0 August 1980
MTU0130 MACASM assembler October 1982
DMXASM 68000 assembler January 1983
License Agreement MTU0130 software
Done: MTU Catalog Spring A2 Spring 1979
Done: MTU Catalog Spring A5 Spring 1980
Done: MTU Catalog Spring A3 Fall 1979
Marketing documents, often with interesting background information
In Bad König, Westenwald, Germany, Matthias Schmitt and his wife have developed a museum dedicated to Technik called TECMUMAS. Mostly retro computers from the early days to the nineteens.
During a visit to the TECMUMAS museum I found a Synertek MDT 1000 development system. Only known to me from an advertisement in Electronics 1980. Matthias allowed me to make detailed photos!
Some pages from Synertek datobboks refer to parts of the MDT 1000 system
Coming soon scan of the MDT 1000 manual, TECMUMAS Matthias will do that soon!
Since the 6532 is in fact a subset of the 6530 (no ROM, more RAM), it seems not too difficult to make a 6532 replacement this way.
The reDIP RIOT is an open source FPGA board which combines the following in a DIP-40 size package:
Lattice iCE40UP5K FPGA
1Mbit FLASH
5V tolerant I/O
The reDIP RIOT provides an open source hardware platform for 6530 RRIOT / MOS 6532 RIOT replacements.
4 february 2025 2025 I have built the PAl-2 kit, now designing and building a I/O card.
This information is based upon the available documentation: User manual, Schematic, BOM.
The PAL-2 is for sale by Liu Ganning at Tindie
Just followed the interactive BOM, passive components first, ICs last.
Nothing special to note, compare yours with the photo on the PAL-2 Tindie site.
Orientation of IC sockets and IC’s, check twice!
Check your soldering joints, not too much sodler, but covered with the right color solder.
And the three slider switches,: the SST keyboard one has a higher slider that the other two!
Please be careful with the Dupont power cables, double check the polarity! If in error: magic smoke!
I do not like the Dupont wires for power, serial, TTY switch. Too easy to make a mistake in the power connection.
I am now designing and building a simple I/O card for the Application connector, experimenters print, point to point wires, male pin connector to PAL-2, on board female connector for USB to Serial, power switch, TTY/Keypad switch.
That may grow later to SD or 1541 or Corsham SD card interfaces.
Video of PAl-2 #4, by Nils, running!
What is a PAL-2?
The PAL-2 is a kit for an SBC in the now large family of KIM-1 clones. Ranging from the Micro-KIM to the PCB exact replica by Eduardo Casino, all share the KIM-1 ROMs, LED display and TTY interface and the 6532 RIOT instead of the 6530 RRIOT.
What makes the PAL-2 unique:
It is a real and complete KIM-1 clone.
Available as a DIY kit with high quality components.
The layout is close to the KIM-1.
The good looking keypad is very close to the KIM-1
Application and Expansion connector with all relevant KIM-1 signals.
Lots of RAM in many configurable options.
Both RRIOTS 6532 on board.
TTY interface on TTL level, USB to TTL adapter included in the kit, quality serial!
Power can come from the USB to TTL adapter or from external 5V supply (same as for the KIM-1)
The PAL-2 differs from a KIM-1
No Audio cassette interface for file I/O circuit, but see below for a solution
Application and Expansion connector as 22×2 pinheader instead of PCB edge connectors
The signals on the Application connector are not all identical: no audio, TTY instead of 20 mA loop, decoding lines added
Not the same size PCB
The PAL-2 differs from the PAL-1:
The many quality improvements and enhancements make the base PAL-2 kit more expensive then a base PAL-1 kit.
If you expand the PAL-1 to the level of a PAL-2 you need to spend money on a motherboard, a RAM 32K, a second RRIOT kit, an RS232 cable and gender changer and a 9V power supply.
Improved keypad, with labels and look of the KIM-1
No need for a Motherboard
No external RAM module required
No external RRIOT required
E000-FFFF can be used freely from ROM expansion
The vectors (Reset, NMI, IRQ) can be placed in external ROM.
RAM decoding
The PAL-2 has a very flexible RAM memory layout, as shown in the next parts of the schematics:
Internal ROM and external ROM
The PAL-2 has a 2K ROM with the KIM-1 monitor. Since there is no audio in and out circuitry, the ROM from 1800-1BFF could be used for other programs, like the KIM Clone by Corsham Technology (Which also did not have the audio circuitry). The 28C16 is easy to program.
One of the first expansions that is to be expected is an external 8K ROM. The decoding for this ROM, e.g. an 28C64 is already present on the connectors and in the decoding circuit.
The decoding signals are 8K7_SELECT (CE on 28C64) and 8K7_ROM (OE on 28C64). Just the 28C64 IC has to be connected to address and data lines.
DIP Switches
The PAL-2 has a full 64K address decoder onboard, while the KIM-1 has only a 5K onboard address decoder for expansion. These two DIP switches on the PAL-2 are designed both to expand the KIM-1’s RAM and to maintain compatibility with its basic configuration.
On the PAL-2, the 4-bit DIP switch enables the onboard K1 to K4 RAM spaces, with each bit controlling 1K of memory. The K1 to K4 naming follows the definitions in the KIM-1 user manual, covering the address range from $0400 to $13FF. If all four DIP switches are set to ON, the entire 5K RAM space becomes available to the system.
The 8-bit DIP switch controls the “big segment decoder,” with each bit corresponding to an 8K memory block. These blocks range from 8K0 to 8K7, with 8K0 ($0000 to $1FFF) being the KIM-1’s default occupied address space. Since the PAL-2 is a KIM-1 replica, if you want to use it as a KIM-1 system, 8K0 must be set to OFF to allow the onboard KIM-1 logic to function. However, if you’re building a completely new system on the PAL-2, you can set 8K0 to ON to bypass the KIM-1’s onboard logic for the lowest 8K of memory.
The 8K1 block starts at $2000, controlling an 8K space beyond this address, and so on. If a bit is set to ON, the KIM-1 system will be able to access the corresponding address space, which will function as RAM. If a bit is set to OFF, the KIM-1 system will still work, but with reduced available address space. When performing expansion or add-on modifications on the PAL-2, you may need to disable certain address spaces to prevent the onboard logic from accessing the RAM chip.
The 8K7 block, representing the highest 8K memory segment, offers additional flexibility on the PAL-2. If 8K7 is set to ON, you can choose how to use this space—either as RAM or ROM—by adjusting the 8K7 SEL switch. For example, if you write a program (such as a tiny OS for the KIM-1) and burn it onto a ROM chip—similar to the well-known Jim’s ROM (but smaller)—you can connect the ROM to the PAL-2 (with some additional hardware, which is still under development). To boot from your ROM chip, use the VECTOR SEL switch to select ROM, allowing the system to retrieve the top three vectors from the ROM chip instead of the onboard KIM-1 ROM.
Application and Expansion connectors
KIM-1 Application connector
Differences on the Application connector with the KIM-1:
AUDIO IN -> 8k7_SELECT
AUDIO OUT LO -> 8K7-ROM
TTY in and out now at TTL level for USB to TTL converter
TTY PTR and KYBD, +1wV, AUDIO OUT LO not connected
This means, even if the edge to pin connector issue is solved, the standard KIM-1 I/O boards will not work for TTY and audio.
The expansion connector is identical to the KIM-1.
KIM-1 Expansion connector
Power supply
Power has to be applied in the standard KIM-1 manner to the application connector Pin 1 = GND, pin A = 5V. Note that reversing these pins will mean the dead of the PAL-2!
Expansion
As a first suggestion for a PAL-2 extension I see a board connected to Application and Extension connectors with:
Power switch
28C64 (or bigger, switchable in 8K chunks) EEPROM
Connector for the USB to TTL
External power connector, switchable between this and USB to TTL connector
TTY/LED keyboard switch
connector for the Application I/O ports PA0-PB7
Power switch
Optional:
Pin connector for PAL-1 Cassette Interface audio board
The KIM-1 has hardware and software in the 6530-003 ROM to save and dump files on audio tape.
Not used by most KIM clone users, so it is not present on the Corsham KIM Clone and the PAL-2.
But it is possible to have the audio in/out with one patch wire between pin 11 of U12D and the application connector!
KIM-1 Audio and TTY circuit
PAL-2 Audio and TTY circuit
On the KIM-1 circuit you can see the audio I/O is seen by the CPU at pin PB7 of the 6530-003. It is either an input or an output under control of the audio routines in the ROM.
The U26 (also present on the PAL-2 as U12d) is an open collector NAND feding PB7. On one input of U26 is PB5 from the 6530/32 (inverted by U16 (KIM-1_ or U10D (PAL-2), on the other is the output of the audio circuit generating TTL pulses from the audio sound input. This way PB7can be used both as input and output.
The PAL-2 and the KIM-1 has on the extension connector the signal PLL(_TEST), which is connected to U126/U12D. This is on the KIM-1 the output of the audio circuit.
So we have audio in (at TTL level) on the PAL-2 covered!
Audio out is available at PB7 at TTL level. With a patch wire between PB7 (or pin 11 of the U12D) to the application connector.
With the PAL-1 Cassette interface we can have the PAL-2 read and write KIM-1 audio cassette files this way. PLL_TEST to TAPE and a wire from PB7 to PB7 is all you need to connect to the Cassette Interface (and GND and +5V ofcourse).
Leaving R9 out of the Cassette Interface may be a good idea, there is already a pullup in the PAL-2 of 1K.
Physical Dimensions
The connector on the PAL-2 is a 2.54 mm pitch 2×22 female pin header connector.
The dimensions of the PAL-2 PCB are 168 mm x 218 mm.
Next two images show the connector, first shows the distance between the two connectors, while the second shows the distance from the PCB edge to the connector’s outer side.
K-1007-1-A
