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Elektor Computing 5 German

Thanks to Martin Seine I have added the German evrsion of Elektor COmputing 5, dedicated to the EC65 systen, Z80 card, 65818 etc.

And have a look at the EC65 Z80 card page also

 

Solid State Tape Device for the (micro)KIM


Willem Aandewiel designed a tape device for the (micro)KIM. With a Wemos D1, ES8266 and ATTiny and some clever software to make the KIM believe a audio cassette recorder is connected.
All details here on Willem’s website.

 

 

The device in action:

Willem has now published the next generation, together with a 32K RAM card, of this device.

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Cassette interface for Micro-KIM

or KIM Clone!

By Timothy Alicie

Demonstrates his  design for a cassette interface for the Micro-KIM single board computer from Briel Computers (a replica of the 1970’s KIM-1 SBC). The original KIM-1 has a built-in cassette interface, but the Micro-KIM replica does not, so I designed and built his own. The design uses a single PIC micro-controller, is very reliable, supports all HyperTAPE speeds, and has the ability to save and play back recorded data into the KIM-1.

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Home-Brew Cassette Interface for Micro-KIM

Design by Timothy Alicie

Demonstrates his design for a cassette interface for the Micro-KIM single board computer from Briel Computers (a replica of the 1970’s KIM-1 SBC). The original KIM-1 has a built-in cassette interface, but the Micro-KIM replica does not, so I designed and built my own.

The design uses a single PIC micro-controller, is very reliable, supports all HyperTAPE speeds, and has the ability to save and play back recorded data into the KIM-1.


From the source of the microcontroller:

All design files (PCB gerbers, source and hex files PIC microcontroller) in this archive.

/*******************************************************************************
* Micro-KIM Cassette Interface, PIC16F6/27A/28A/48A Implementation
*
* The original KIM-1 uses a PLL and a comparator to implement the receive
* path of the cassette interface. These two parts have been replaced by
* this implementation which runs on a PIC microcontroller.
*
* The KIM-1 cassette format encodes each bit using two tones:
* 1) A high-frequency tone of 3623.188 Hz (1.5X the low-frequency tone)
* 2) A low-frequency tone of 2415.459 Hz
*
* Each bit is broken up into three periods, each of which is 2.484 ms long,
* during which either the low frequency or the high frequency tone is played.
*
* The high frequency tone is always played in the first time period, and the
* low-frequency tone is always played in the last time period. A bit is encoded
* as logic ‘1’ by playing the low-frequency tone in the middle time period, and
* a logic ‘0’ by playing the high-frequency tone in the middle time period:
*
* Logic 1: encoded as HiFreq-LoFreq-LoFreq
* Logic 0: encoded as HiFreq-HiFreq-LoFreq
*
* The KIM-1 cassette interface uses a PLL tuned to distinguish between the
* high and low frequency tone. The output of this PLL is then fed into a
* comparator to generate a logic ‘1’ whenever the high frequency is detected,
* and a logic ‘0’ whenever the low frequency is detected. This logic signal
* is analyzed by the KIM-1 to reconstruct the bit-stream stored on the cassette
* tape. Each bit begins with a low-high transition, and the bit value can be
* determine by the timing of the falling edge generated by the high-frequency
* to low-frequency transition within each bit.
*
* The job of the PIC KIM cassette interface implementation is to perform the
* same function of the original PLL and comparator: analyze the input signal,
* and generate a logic ‘1’ output whenever the high frequency is detected, and
* a logic ‘0’ output whenever the low frequency is detected. The implementation
* is rather simple: analyze the timings of zero-crossings detected in the input
* signal, use this information to determine the frequency of the input signal,
* and generate the output signal based on if the input signal is closer to the
* high frequency, or closer to the low frequency.
*
* The original KIM-1 tape algorithm uses a bit period of 7.452 ms, which is
* three periods of 2.484 ms each. Within each sub-period, exactly 9 cycles of
* the high frequency tone can be played, or exactly 6 cycles of the low
* frequency tone can be played.
*
* Jim Butterfield popularize an alternative called HYPERTAPE, which reduces
* these periods to speed up the data by a factor of 2X, 3X, or 6X. The only
* difference between the HYPERTAPE implementation and the original implementation
* is that the sub-bit periods are reduced. The 2X and 6X sub-bit periods are
* reduced such that a non-integer number of cycles of the high and low frequency
* tones are played within each sub-period. Thus, the PIC detects the frequency
* based on half-cycles to fully-support HYPERTAPE.
*
* Interesting facts:
*
* Original KIM-1 cassette bit-rate: 134.2 bits/sec (402.6 baud, 3 symbols/bit)
* HYPERTAPE 6X bit-rate: 805.2 bits/sec (2415.5 baud, 3 symbols/bit)
*
* Each data byte is represented as two ASCII hex digits, so the effective data
* transfer rate is 8.4 bytes/sec for the original speed, or 50.3 bytes/sec for
* HyperTAPE x6.
*
* High frequency tone: 3623.188 Hz, or 0.276 ms/cycle
* Low frequency tone: 2415.459 Hz, or 0.414 ms/cycle
* Center frequency: 2898.551 Hz, or 0.345 ms/cycle
*
* Frequency detection based on half-wave zero-crossings:
* High frequency tone: zero-crossing every 138 us
* Low frequency tone: zero-crossing every 207 us
*
* Separation between high-frequency and low-frequency zero-crossing: 69 us
* Threshold between high and low-frequency zero crossing: 172.5 us
*
* Implementation Notes:
*
* The bi-color LED lights red when an input signal is present, but it does
* not contain the correct frequencies to be a valid KIM-1 bit stream, for
* example, voice input. The bi-color LED lights green if the input signal
* contains the correct frequencies to be a valid KIM-1 bit stream. While
* receiving data, the green LED should be lit solid to ensure reliable data.

* Comparator 1 (CMP1) is used to detect signal zero-crossings by adding a bias
* to the input AC signal of Vcc/2. The bias is used as the V- comparator input.
*
* RB4 is used to monitor the PB7 line to/from the KIM-1. In audio-output mode,
* (dumping to a tape), the KIM-1 drives this line, so we can use it to detect
* audio-output mode and light the LED when the KIM-1 is dumping data.
*
* Timer 0 (TMR0) is used to light the LED indicators for a certain time period.
*
* Timer 1 (TMR1) is set up to count at 1.0 MHz, and it is used to precisely
* measure the time between zero crossings.
*
* Copyright Timothy Alicie, 2017, Timothy Alicie
*******************************************************************************/

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G.Eisenack Programmieren von Mikrocomputern CPU 6502 Skriptum

New book added tot the KIM-1 Books resources: (thanks netzherpes)

G.Eisenack Programmieren von Mikrocomputern CPU 6502 Skriptum

Memory Plus manual and photo

Thanks to Dirk Dral, an old friend from the days of the Kim Kenner Club, with articles in KIM Kenner 13 and 16 (traffic control, cassette Interface) I have published a quality photo of his Memory Plus and a quality scan of the manual.

He also sent me photosof his KIM-1 and the Radio Bulletin RAM and EPROM cards.

PAL-1 extensions

Motherboard 6 slot, 32K RAM , second 6532 board, now on Tindie for the PAL-1 (and Micro-KIM)

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NOP testers

I built two NOP testers, simple standalone devices to do a simple sanity check test if this CPU is at least doing something that can be expected. Not a thorough test of speed, instructions, all address lines or datalines or control lines. 

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CPU NOP testers

While building the Retro Chip Tester, designed by Stephan Slabihoud, and documented on his 8bit-museum website, I noticed Stephan also designed CPU NOP testers and made designs as gerbers and BOM available. With the PCB of the Retro Chip tester I laso bought the PCB’s for 6502 and Z80 NOP tester from him. NOP testers are very simple test devices and in no way a real CPU stress test. Enough to discover if the IC is not a fake or severely damaged and not fit to be tested in a real system.
The idea of NOP testers is not new, for example Lee Davison documented his NOP tester for the 6502 here.

Stephan made the NOP testers standalone devices. Besides the socket for the CPU to test a clock signal is generated with a 555, a push-button does the reset, the minimal of control lines is connected to ground or puleld high, power is supplied with a USB connector.

The clock oscillator has a very low frequency, so you can see the address lines change by observing LEDs connected. This means the NMOS 6502 and Z80 are operated way below their minimal frequency, e.g. 100KHz for a 6502. The CMOS versions are static and can be driven with this low frequency.
In my experience with these testers is that the NMOS versions of 6502 and Z80 do work with this tester though, but I have seen good 6502’s start off well but after a minute crashed with all LEDs flashing in the tester. So not a definite test for NMOS! An interesting modification would be to have a higher clock frequency (1MHZ at least) and inspect all the address lines with an oscillosope.

Read the original articles and download Gerbers and BOM’s from the 8bit-museum.

6502 NOP Generator

Used in a 6502 NOP generator , a 6502 CPU only executes NOP commands (No Operation). The low eight address lines can be observed with the aid of LEDs. If the CPU executes the NOPs, the addresses should be continuously incremented. This does not allow a complete test of the CPU, but at least a quick-n-dirty check.

The 6502 NOP generator in action:

The 6502 NOP generator supplies the opcode 0xEA, which corresponds to a NOP for the 6502. After a reset, the 6502 NOP generator starts to count from address 0xEAEA (after a reset the CPU reads the real start address from addresses 0xFFFC-0xFFFD and since this always reads 0xEA, this is 0xEAEA). The LEDs should start counting at 11101010.

It is very nice to see how after the reset the addresses 0xFFFC and 0xFFFD are accessed first (before that a little initialization of the CPU), in order to then count from 0xEAEA (LEDs: FC, FD, E9, E7, EA, E9, FD, [FF] FC, [FF] FD, [EA] EA, EB, EC, ED, EE, EF, F0, F1 .., the upper 8 bits added in square brackets for understanding).

Changes for WDC65C02

While the 6502 NOP Generator has been designed for the 65C02 and 6502 pinout, it can be modified to work with the still available WDC65C02 variant. Differences between the variants are minor but essential:

VPB Vector-Pull output Pin1 must be left open, on the 6502 and 65C02 this is the (second) Ground pin, On the PCB pin 1 is connected to ground, easy to cut track, see the photo below.

Pin 36 BE (Bus Enable) Connect a resistor 10K to VCC. Easy to add on the bottom of the PCB. pin 36 is NC (Not Connected) on 6502 and 65C02.

The latest gerbers on teh site of 8bit-museum have these modifications!

Cut the track on the PCB in the red ring, GND to Pin 1

Gerber view in Kicad tool

V.3, has a jumper for Gnd on Pin 1 or not, and a 10K resistor on pin36 BE

Z80 NOP tester

When used in a Z80 NOP generator , a Z80 CPU only executes NOP commands (No Operation). The low address lines can be observed with the aid of eight LEDs. If the CPU executes the NOPs, the addresses should be continuously incremented. This does not allow a complete test of the CPU, but at least a quick-n-dirty check.

The NOP generator presented here only works with Z80 CPUs. Since the CPU is clocked very slowly, far outside the specification, it is quite possible that an actually functional CPU does not work with the NOP generator. The way it works is very simple: The data lines are pulled to ground by pull-down resistors, so that the CPU reads a NOP (opcode 0x00) when the memory is read. After a reset, the CPU starts executing these commands from address 0.

Gerber view in Kicad tool

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CM630P 6502 clone

CM603P, a 6502 by MICRO ELEKTRONIKA BULGARIA. Used in Apple II clones like Pravetz-82 and IMKO-1 and Oric Atmos clone Pravetz-8D. Not an official 6502 licensed CPU. Pinc compatible, can be used in 6502 systems without issues.

Added to my 65XX IC collection.