While building the Retro Chip Tester, designed by Stephan Slabihoud, and documented on his 8bit-museum website, I noticed Stephan also designed CPU NOP testers and made designs as gerbers and BOM available. With the PCB of the Retro Chip tester I laso bought the PCB’s for 6502 and Z80 NOP tester from him. NOP testers are very simple test devices and in no way a real CPU stress test. Enough to discover if the IC is not a fake or severely damaged and not fit to be tested in a real system.
The idea of NOP testers is not new, for example Lee Davison documented his NOP tester for the 6502 here.
Stephan made the NOP testers standalone devices. Besides the socket for the CPU to test a clock signal is generated with a 555, a push-button does the reset, the minimal of control lines is connected to ground or puleld high, power is supplied with a USB connector.
The clock oscillator has a very low frequency, so you can see the address lines change by observing LEDs connected. This means the NMOS 6502 and Z80 are operated way below their minimal frequency, e.g. 100KHz for a 6502. The CMOS versions are static and can be driven with this low frequency.
In my experience with these testers is that the NMOS versions of 6502 and Z80 do work with this tester though, but I have seen good 6502’s start off well but after a minute crashed with all LEDs flashing in the tester. So not a definite test for NMOS! An interesting modification would be to have a higher clock frequency (1MHZ at least) and inspect all the address lines with an oscillosope.
Used in a 6502 NOP generator , a 6502 CPU only executes NOP commands (No Operation). The low eight address lines can be observed with the aid of LEDs. If the CPU executes the NOPs, the addresses should be continuously incremented. This does not allow a complete test of the CPU, but at least a quick-n-dirty check.
The 6502 NOP generator in action:
The 6502 NOP generator supplies the opcode 0xEA, which corresponds to a NOP for the 6502. After a reset, the 6502 NOP generator starts to count from address 0xEAEA (after a reset the CPU reads the real start address from addresses 0xFFFC-0xFFFD and since this always reads 0xEA, this is 0xEAEA). The LEDs should start counting at 11101010.
It is very nice to see how after the reset the addresses 0xFFFC and 0xFFFD are accessed first (before that a little initialization of the CPU), in order to then count from 0xEAEA (LEDs: FC, FD, E9, E7, EA, E9, FD, [FF] FC, [FF] FD, [EA] EA, EB, EC, ED, EE, EF, F0, F1 .., the upper 8 bits added in square brackets for understanding).
Changes for WDC65C02
While the 6502 NOP Generator has been designed for the 65C02 and 6502 pinout, it can be modified to work with the still available WDC65C02 variant. Differences between the variants are minor but essential:
VPB Vector-Pull output Pin1 must be left open, on the 6502 and 65C02 this is the (second) Ground pin, On the PCB pin 1 is connected to ground, easy to cut track, see the photo below.
Pin 36 BE (Bus Enable) Connect a resistor 10K to VCC. Easy to add on the bottom of the PCB. pin 36 is NC (Not Connected) on 6502 and 65C02.
The latest gerbers on teh site of 8bit-museum have these modifications!
Cut the track on the PCB in the red ring, GND to Pin 1
Gerber view in Kicad tool
V.3, has a jumper for Gnd on Pin 1 or not, and a 10K resistor on pin36 BE
Z80 NOP tester
When used in a Z80 NOP generator , a Z80 CPU only executes NOP commands (No Operation). The low address lines can be observed with the aid of eight LEDs. If the CPU executes the NOPs, the addresses should be continuously incremented. This does not allow a complete test of the CPU, but at least a quick-n-dirty check.
The NOP generator presented here only works with Z80 CPUs. Since the CPU is clocked very slowly, far outside the specification, it is quite possible that an actually functional CPU does not work with the NOP generator. The way it works is very simple: The data lines are pulled to ground by pull-down resistors, so that the CPU reads a NOP (opcode 0x00) when the memory is read. After a reset, the CPU starts executing these commands from address 0.
CM603P, a 6502 by MICRO ELEKTRONIKA BULGARIA. Used in Apple II clones like Pravetz-82 and IMKO-1 and Oric Atmos clone Pravetz-8D. Not an official 6502 licensed CPU. Pinc compatible, can be used in 6502 systems without issues.
In the Elektor Specials Elektor bus based systems were presented that could be used to build more advanced computers, based on the 6502, Z80 of 65816.
Several names were used for systems, like EC65 and Octopus and you see in these pages many references to these cards, like DOS65, Elektor articles and books
See below for the Elektor Specials with EC65 etc articles.
From Martin Seine I have received the source of the EC65 ROM and the system disk of the EC65 system
Disassembled, sorted and and somehow aligned the original SAMSON EPROM. The assembler file is here. It will compile byte identical with ca65. All uppercase labels match the documentation he found. The lowercase labels are made up by Martin, because they are needed in there. There is a disassembler in the monitor rom, which he did not analyze and hence the disassembly is just strong bytes in that section.
Martin has recovered some original EC65 disks. Here the original disk#5, which is the „System Disk Loys“ as HFE image, which will run on EC65 with Gotek FlashFloppy. Martin has now a running EC65 with original system disk. The HFE is the 80-track version and a double side image, but it works as one side as well.
Adding I/O devices that don’t need much address space. On the KIM-1, the space from 1400-17FF is grouped into the K0 block but only 17xx are used, leaving 1400-16FF open for use. To decode that range into four blocks of 256 bytes is easy using a single chip and a few signals from the KIM Clone expansion bus:
Everyone has a 74LS138 in their parts collection, so just connect a few signals from the expansion bus and use one of the three signals from the 138 to decode which block you want to use. Use the A0-A7 address lines to decode into smaller pieces.
While testing the KIM Clone I/O Board I was using a real ASCII terminal and everything was working exactly as it should. After the board was in product a dedicated tool was written to run complete tests of the board and the serial port was no longer receiving data.
As it turns out, it is possible to set the various jumpers on the board so that the DCD line on the 6850 is floating, and it tends to float to a state where it ignores incoming data. My test jig simply loops back pins 2 and 3, leaving DCD unconnected.
The easiest solution is to pull the jumper off JP8, then place it between pins 6 and 7 on JP10. This forces the DCD to ground, which allows the receiver to work as expected.
Depending on your application, whatever is connected to the DB-9 might pull DCD to the active state which also allows the receiver to work properly.
Future revisions of the board will have a pull-down resistor on both DCD and CTS so unconnected inputs will default to the proper levels for normal operation of the ACIA.
Using I/O lines
Like the original KIM-1, there are 16 I/O lines on the KIM Clone that can be used for your own projects. They are brought to the connector labeled “SD SYSTEM” along the top edge of the board and were meant to plug into one of our SD Card Systems for program storage. However, they are general purpose I/O lines which can be freely used for other things if the SD system is not used.
This is a portion of the schematic showing which pins on the 6532 are connected to which pins on the connector:
Don’t worry about the signal names associated with the various lines, they are the names of those signals when an SD Card System is attached.
As you can see, there are 16 IO lines, 2 ground lines, and 2 lines with +7.5… if you want to draw power from this connector for TTL/CMOS circuits then you need to add your own +5 volt regulator! D2 prevents back-feeding power from the connector back into the KIM Clone.
On the circuit board, pins 1 and 2 are labeled but are covered by the connector, so here is a reference:
All of the odd numbered pins are on the “bottom” row while even numbered pins are on the top. Ie, the top row has pins 2, 4, 6, etc, while the bottom row has 1, 3, 5, etc. Displaying the circuit board traces on the bottom layer of the board you can clearly see the ground and power lines connected to the pins on the far right:
To program the chip you basically need to set the direction of each pin of the I/O port of interest (Port A or Port B), then set the data or read the data. The base address of the chip is 1700 (hex). There are four registers:
Address
Use
1700
Data register A
1701
Data direction register A. Setting a bit to 1 makes it an output bit, 0 makes it an input.
1702
Data register B
1703
Data direction register B. Setting a bit to 1 makes it an output bit, 0 makes it an input.
An Example
I needed to test experimental address decoder logic and found it was easier to just plug it into the I/O ports and write some code on the KIM Clone to simulate the addresses and display what the decoder logic did:
Port A simulates address lines A11-A16 and port B has the three decoder outputs (/RAM, /IO, /EEPROM). A small program simulates all possible values of the five address bits, displays the address, reads the decoder inputs and then displays which are active. In about an hour I was able to fix one minor bug in the decoder design and perform a full unit test on how it works. Certainly not a fancy example of using I/O ports, but sometimes it far faster to build a small circuit and use software to test it rather than building a lot of hardware and manually debugging it all.
A new KIM-1 clone kit in 2021, the PAL-1. In fact, this is a Micro-KIM clone, which is a KIM-1 clone .. Look and specs are like the Micro-KIM, with some improvements like larger keys and a very affordable price. Motherboard, 32K RAM, second 6532 board, RAM board, ROm board, Cassette board, a full KIM-1 and more compatible system.
Designer and seller is software engineer, Liu Ganning, KJXZZ, from Shenzhen, Guangdong, China
The PAL-1 has its own discussion platform at google groups. For software: se the KIM-1 software page, as the PAL-1 is a KIM-1 with lots of memory! PAL-1’s difference
First, PAL-1 is a kit, you can assemble it, test it and run it all by yourself —— an unique experience！
The PAL-1 addressing mode is completely implemented in accordance with the design of KIM-1, so it is compatible with most programs developed on KIM-1.
PAL-1 has 2K bytes ROM (complete KIM-1 Monitor), 5K bytes RAM, one 6532 RIOT chip on board, provides two 8-bit bidirectional I/Os, these I/Os are mainly used to support 23-key keyboard input and drive 6 seven-segment LED displays. In addition, PAL-1 also provides RS232 serial port to support terminal operation and 40-pin expansion port for future upgrade. The TTY/RS232 interface and expansion interface pinout uses the design of Rich Dreher and Vince Briel (MicroKIM compatible).
Besides the PAL-1 also a 6 slot motherboard, a 32K RAM board and a RIOT board (the second 6532 making it a complete KIM-1) and a cassette interface baord are available. A ROM boards adds many programs like programming languages Basic, Forth etc.
The main differences between PAL-1 and KIM-1 are illustrated by the following two figures in the “KIM-1 User Manual”.
PAL-1 absence half I/O and Timer (red) Picture 11 (see the RIOT board how to add this!)
PAL-1 onboard RAM increased to 5K (all green spaces are available) Picture 10 What is included
The PAL-1 Kit includes mainboard PCB, ICs, pre-programmed ROM, passive components, sockets & headers.
Print version BOM, Pinout, Schematic.
The two following images show how to adapt the PAL-1 to a TTL USB interface instead of RS232. also supplying power from USB.
Modification of ROM board 1.0 for 28C256 EEPROM
The ROM card v1.0 is designed for using 27C256 and 27C512 EPROM, but these UV-erase chip will need much patient when you’re doing a lot of ROM program. So the PAL-1 got a new version ROM card, v1.2, to support the more convenience EEPROM, the 28C256.
Even the v1.0 ROM card designed for the 27Cxxx, you can also use the 28C256 on it. Just one soldering work need to do, populate the high 32K switch using a switch (like K3-2235D-F1) or 3-pin 2.54mm pin header (solder at the inner side of the high 32K switch).
When you need to using a 28C256, you can set and keep the low 32K switch to HIGH, then using the high 32K switch/jumper to select the low 16K bank or the high 16K bank of 28C256 just like normal.
A second RAM board can be modified to add 16K extra.
Modify a 32K RAM card for the upper RAM area. Just need to cut 1 wire and solder 2 jumper wires like below:
The KIM ROM needs the highest area of 64K for the vectors, so the Exxx to FFFF cannot be decoded with the second 32K RAM card.
We can use $A000~$DFFF (16K) more RAM with the second RAM card installed.
