EagleCAD schenatics archive download
Imported in Kicad, exported as SVG images on this page:
Logic concept
Clock Generator
Reset
RS0
A0
A9
CS1 Latch
RW
<
PB7 driver/buffer
a href="http://retro.hansotten.nl/wp-content/uploads/2021/11/6530-004_dissect_9-6530-004_dissect_9.svg">
PB6 driver/buffer
PB0 driver/buffer
PLA
Some logic
I/O control
I/O logic, Bit 7
Timer control
Predivider
Timer (don countyer)
RAM row buffer/driver
ROM
See also:
History of the TIM in the Jolt
Images of the Jolt
Above photos by The National Museum of American History.
Photos from https://vintagecomput...
A Jolt Replica
Scott LaBombard started many years ago on a replica of the Jolt. Quite a challenge, since only photos are known.
He ...
SM Baker AIM 65 projects
Scott Baker Rockwell AIM-65 Projects
A number of interesting AIM 65 projects found on SM Baker's github page (thanks ...