EagleCAD schenatics archive download

Imported in Kicad, exported as SVG images on this page:

Logic concept

Clock Generator

Reset
RS0

A0

A9

CS1 Latch

RW
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PB6 driver/buffer

PB0 driver/buffer

PLA

Some logic

I/O control

I/O logic, Bit 7

Timer control

Predivider

Timer (don countyer)

RAM row buffer/driver

ROM