The RRIOT in CBM disk drives are only different in the ROM contents The rest is as follows:
(information contributed by Martin Hoffmann-Vetter and Nicor De Vries)
- Pin 18 is PB6 (no CS1)
- Pin 19 is CS2 (no PB5) active low
- Pin 17 (PB7/IRQ) has no Pullup
- ROM is in $FC00 to $FFFF (RS0=0, CS1=X, CS2=1)
- RAM is in $0000 to $003F (RS0=1, CS1=X, CS2=0, A9=0 A8=0, A7=0, A6=0)
and also $0100 t0 $013F RS0=1, CS1=X, CS2=0, A9=0, A8=1, A7=0, A6=0) - I/O is on $0080 to $00BF (RS0=1, CS1=X, CS2=0, A9=,0 A8=0, A7=1, A6=0)
Logic of addressing:
RS0 CS1 CS2 A9 A8 A7 A6 ROM 0 X 1 - - - - RAM 1 X 0 0 X 0 0 IO 1 X 0 0 0 1 0
Via an adapter board Commodore reused older 6530’s with new firmware by disabling the built in ROM and adding a 2716.
See Zimmers Commodore archive. Note that not just any 6530 can be used in this way, only the 6530’s from the Commodore diskdrives.A more general approach with a 6532 is described here.
6530 replacement for Commodore drives
Taken from 6530 replacement by Ruud Baltissen
What is it?
Various IEEE dual floppy drive have a 6530 on board. This is a masked programmed IC, for details read this document first. There is only one problem with this IC: if it breaks down, new ones aren’t available anymore and second handed ones are rare. Good reasons to develop a replacement.
Attention: Commodore produced various 6530s, for example the ones used in the KIM-1. This design cannot be used to replace these ones, it is only meant to replace the 6530 in the following drives:
– 2040
– 3040
– 4040
– 8050
– 8250
– 8250-LP
– SFD-1001
First some credits
My (Ruud Baltissen) prototype did not work so I asked the CBM-Hackers for help. Gerrit Heitsch, Gordon Steemson and Martin Hoffmann-Vetter both pointed me to some critical errors in the design. Thank you very much!
The design
The main reason for developing a 6530 replacement was running out of 6530 spares. Unfortunately it wasn’t as simple as with building the KIM-1 replica.
The 6530 can be divided in three parts:
– the ROM
– the RAM
– the I/O
The design: the ROM
One of the great helps here was this schematic found at www.zimmmers.net. For selecting the ROM, the input /RS0 must be set to (L) and the input /CS2 must be set to (H). So I used /RS0 in the first place to enable the EPROM on my PCB by tying these inputs directly to /RS0.
I noticed that the 8250LP and SFD-1001 have a little PCB on the place of the 6530. On this PCB you will find a 6530, an EPROM and a 74LS04. The reason for this PCB was that Commodore needed to update the ROM for one or another reason. And probably it was cheaper to create this PCB than producing new 6530’s.
Anyway, the CS input of the EPROM has been connected to /RS0 of the original socket. The /RS0 input of the original 6530 has been connected to +5V. This only confirmed that my idea how /RS0 should be used was correct.
One gate of the 74LS14 is used to invert PHI2 and the result is used to control the OE input of the EPROM. This construction is needed because there are two 6502s on the main board. Each 6502 has its own address bus but both 6502s share the same data bus. This is made possible because the second 6502 runs on the inverted clock of the first one. The inverted PHI2 on the OE input makes sure that the EPROM only outputs its data when the right 6502 is in command.
The design: the mapping of the RAM and the I/O
If you have another look at the schematic you will see that both the 6532 and the 6522 share the same Chip Select line coming from output 0 of the on board 74LS42. My first impression: quite confussing!
Most helpfull after all appeared to be the disassembly I made of the disk controller of the 8250. The memory map for the disk part looks like this:
$0000 – $0029 : 6530 RAM
$0040 – $004D : 6522 registers
$0080 – $008F : 6530 registers
$0100 – $01FF : possible stack
We know the 6530 has 64 bytes of memory on board so we can assume:
$0000 – $003F : 6530 RAM
The input /RS of the 6532 tells it when to select RAM or I/O. Connecting it to A7 makes sure that the RAM and the I/O of the 6532 fit in the above table.
The I/O and memory of the 6530 are mapped to the first KB, $0000 – $0400. Having found no further decoding, it means everything should be mirrored every 256 bytes. So the memory mapped to $0000 – $0040 should also appeare at $0100 – $013F. And this is confirmed by the source code: the Stack pointer is set at $3F.
Then what about the 6522? Here we run into a very strange thing: as said before, the 6522 shares the Chip Select line for its negative /CS input with the 6530. The 6522’s positive CS input is connected to address line A6. This means that the 6522 is only active within the range $0040 – $007F, which is confirmed by the disassembly. Due to mirroring it is active within $00C0 – $00FF as well. And further it is also mirrored every 256 bytes within the first KB, just like the 6530.
And now the puzzling thing: when the range $0040 – $007F (read: 6522) is selected, the 6530 is selected as well and yet there is no conflict. Conclusion: a circuit inside the 6530 takes care of not selecting the 6530 for this range.
So we must take care that the 6532 is not selected when the 6522 is. This is realized by inverting A6 and connecting the result to the CS1 input of the 6532.
The design: the I/O
The internal mapping I/O of the 6532 is not the same as the mapping of the I/O of the 6530. For exact details, please see the page about the KIM-1 clones. To make things work the original idea was to invert address line A4 towards the 6532. Although this will work under normal circumstances, it won’t the moment a program addresses a mirror address. The OR gates IC4c and IC4d take care of that.
Maybe you noticed the connection between PB7 and IRQ, I read about that construction in some documents I received with my KIM. I haven’t any idea if this is present in the 6530 for drives. So far I my drives functions fine with it.
The schematic
I think the only explanation that is needed is about the wiring of the EPROM. All unneeded wires are wired to +5V. This enables you to use any EPROM from 2716 to 27512. The original file you will need is only 1 KB. You have to program it in top 1 KB of the EPROM. If using a 2764 it must be programmed in $1C000/$1FFFF. You will find the binary here.
Attention: the ROM of the SFD-1001 is 2 KB, you should only use the first 1 KB. Check this with a tool! (for example: DEBUG under DOS)
The Eagle schematics as ZIP file.
Analysis of the 6530 replacement circuit by Ruud Baltissen
Nico de Vries has some further insights and improvements on this design.
Document version: September 14th 2025
Author: Nico de Vries (Audioniek)
In this document an analysis of the circuit to replace a 6530 in a Commodore IEEE dual floppy disk drive published by Ruud Baltissen (see http://www.baltissen.org/newhtm/6530repl.htm) is given. That circuit makes use of the similarities between the 6530 and 6532 ICs, to replace the former with the latter while adding an EPROM and some (primitive) address decoding.
The 6530 RRIOT
The 6530 is (for the era it was created) a rather complex device, containing 64 bytes of RAM,1 kbytes of ROM, two 8 bit I/O ports and a timer. What makes the part more mysterious is the fact that parts of it are mask programmable; they are defined on the chip level when the chip is manufactured. After studying the result of one being decapped (see https://www.forum64.de/index.php?thread/117122-mos6530-mcs6530-004-aka-tim-dissected/) the following parts seem to be mask programmable:
• The polarity of the ROM select pin RS0;
• The address decoder for the internal RAM;
• The address decoder for the I/O ports and timer;
• The function of pin 18: I/O pin PB6 or chip select CS1 (including its polarity);
• The function of pin 19: I/O pin PB5 or chip select CS2 (including its polarity).
Please note that the function of pin 17 (PB7 or IRQ) is determined in software and is not a mask option of the 6530.
The Commodore IEEE dual floppy drives
Analysis of the schematic diagrams and the code running in the ROM of the 6530 has yielded the following information:
- Pin 4 (RS0) is connected to an active low output of a 74LS42 decoder in all models. The 74LS42 decoder provides an active low for the address area $FC00 through $FFFF (A10, A11 and A12 are all high) See Note 1 below. Pin 4 must be active low then. In the rest of this document it is referred to as /RS0;
- Pin 17 is wired to the IRQ input of a 6502 or 6504 CPU, as well as the IRQ pin of a VIA. That pin is clearly used as IRQ pin, and not as an I/O pin. In addition, the ROM code also has IRQ routines;
- Pin 18 is not connected in the 8050 and 8250 disk drive, but is in the 2040, 3040 and 4040 models. It is therefore used as an I/O pin, not as a chip select;
- Pin 19 is connected to an active low output of a 74LS42 decoder in all models. The 74LS42 decoder provides an active low for the address area $0000 through $03FF (A10, A11 and A12 are all low, see Note 2). Pin 19 must be an active low chip select /CS2 then;
- The I/O in the ROM code is addressed at $40-$4F (this is the aforementioned VIA as its active high CS1 pin is connected to A6, and its active low chip select is shared with /CS2 of the 6530) and $80-$8F (the I/O and timer in the 6530). As the schematic diagram shows, the VIA is incompletely decoded with A4, A5, A7, A8 and A9 being don’t care. In order to avoid a conflict with the VIA, the mask programmed I/O address decoder in the 6530 must at least use /A6. It is quite possible the address decoder for the I/O in the 6530 is set to /CS2 * /A4 * /A5 * /A6 * A7 */A8 * /A9, which would lead to the I/O in the 6530 being decoded fully without mirrors, thus avoiding a conflict with the VIA, see Note 3;
- Because the schematic diagrams reveal no additional RAM apart from the shared RAM at $400 and further, the RAM is used as zero page (location $00 through $29 in the 8050). In addition, the RAM in the 6530 must also be used as stack, as IRQs are used in the code, as well as JSR instructions. Apparently the same area is at least mirrored into page one, to give the CPU a stack area. This is confirmed in the code, as the stack pointer is initialized at $3F (the highest possible 6530 RAM address, the 6502/6504 CPUs have a down going stack pointer). The mask programmed address decoder for the RAM in the 6530 is therefore set to access the RAM at least at $0000-$003F as well as $0100-$013F, making A8 don’t care (some 6530 data sheets specifically state that A8 is don’t care for RAM access). In order to avoid a conflict with either the VIA or the internal I/O A6 and A7 need to be low when accessing the RAM. A possible condition is /CS2 * /A6 * /A7* /A9, see note 4, which would lead the RAM being at $0000-$003F, with one intended mirror at $0100-$013F to give the CPU stack space. Note that the stack pointer cannot be set to $FF as $1FF is a mirror of a VIA register.
Note 1
In the 2040/3040/4040 models a 6504 CPU is used, that does not have the address lines A13, A14 and A15. In the 8050 and 8250 models a 6502 is used but the lines A13, A14 and A15 are not connected, yielding the same result: the three address lines mentioned are don’t care, yielding 8 mirrors. The CPU however fetches its IRQ, Reset and NMI vectors from the ROM, so it is using the mirror at $FC00-$FFFF.
Note 2
In the 2040/3040/4040 models a 6504 CPU is used, that does not have the address lines A13, A14 and A15. In the 8050 and 8250 models a 6502 is used but the lines A13, A14 and A15 are not connected, yielding the same result: the three address lines mentioned are don’t care.
Note 3
This needs further confirmation regarding the mirror addresses being absent or not.
Note 4
The presence of A9 in the condition is a guess. If it is absent, the RAM would be mirrored at $0200-$023F and $0300-$033F as well. This needs confirmation.
The replacement circuit
The schematic as published is given in appendix A. In the replacement circuit,
the 6532 RIOT is connected as follows
A0 - 3 : A0 - 3 of 6530 A4 : A4 + A7 of 6530 (+ is logical OR, not arithmetic addition) A5 : A5 of 6530 A6 : GND (line is not used as A6 is part of the chip select condition) CS1 : /A6 of 6530 /CS2 :/CS2 of 6530 /RS : A7 Dn : Dn of 6530 and EPROM PHI2 : PHI2 of 6530 R/W : R/W of 6530 RES : RES of 6530 IRQ : PB7 of 6532 plus PB7/IRQ of 6530 PAn : PAn of 6530 PB0 - 4 : PB0 - 4 of 6530 PB5 : not connected (PB5 of 6530 is used as /CS2) PB6 : PB6 of 6530 PB7 : /IRQ of 6530 and 6532 (PB7 is programmed in 6530 ROM as IRQ pin)
EPROM is connected as follows
A0 - A9 : A0 - A9 of 6530 A10+ : Vcc (code must reside in top of EPROM) /CS : /PHI2 of 6530/6532 /OE : /RS0 of 6530 Dn : Dn of 6530/6532
Based on the connections mentioned above, access conditions are then as follows.
EPROM
• /RS0 of 6530 is low AND PHI2 is high.
Remarks:
1. /OE (not /CS) is connected to /RS0 of 6530. The EPROM enters low power standby only with PHI2 low instead of not being addressed;
2. R/W is don’t care. The EPROM is also accessed if something writes to ROM (causing a bus conflict).
Suggestion: swap /OE and /CS to reduce energy consumption and include R/W in the decoding.
Conclusion: In the replacement circuit, ROM is accessed in the same way as original, apart from the fact it can be written to (which probably does not happen).
I/O of 6532
An interpretation of the datasheet is that I/O is accessed with CS1 is high, /CS2 is low and /RS is high.
(Remark: the MOS Technology sheet the author has does not explicitly state this, but apparently
assumes so). Here it goes:
• CS1 is high when A6 is low (because of the inverting IC4B);
• /CS2 is low when /CS2 of 6530 is low;
• /RS is high when A7 is high.
In the replacement circuit the condition is therefore A6=A10=A11=A12=low and A7=high.
Written out in binary (the Y’s are the valid bits to address the various registers):
0 1 2 3 4 5 6 7 8 9 A B C D E F Y Y Y Y X X 0 1 X X 0 0 0 X X X -> condition Y Y Y Y 0 0 0 1 0 0 0 0 0 0 0 0 -> true access at $008X Y Y Y Y 1 0 0 1 0 0 0 0 0 0 0 0 -> first mirror at $009X Y Y Y Y 0 1 0 1 0 0 0 0 0 0 0 0 -> second mirror at $00AX Y Y Y Y 1 1 0 1 0 0 0 0 0 0 0 0 -> third mirror at $00BX Y Y Y Y 0 0 0 1 1 0 0 0 0 0 0 0 -> fourth mirror at $018X... Y Y Y Y 0 0 0 1 0 0 0 0 0 1 0 0 -> mirror at $208X... Y Y Y Y 1 0 0 1 0 0 0 0 0 0 1 0 -> mirror at $409X... Y Y Y Y 0 1 0 1 0 0 0 0 0 0 0 1 -> mirror at $80AX... Y Y Y Y 1 1 0 1 1 1 0 0 0 1 1 1-> last mirror at $E3BX
In the code PB7 is defined as an input. This is a requirement to be able to use the 6530 pin as IRQ
pin. Just as well: despite of the connection to /IRQ, the interrupts still work. In case the 6532 pin
would be an output they would not. An improvement is to remove the connection between PB7 and
/IRQ on the 6532.
RAM of 6532
According to the datasheet RAM is accessed with CS1=high, /CS2 is low and /RS is low, so:
• CS1 is high when A6 is low (because of the inverting IC4B);
• /CS2 is low when CS2 of 6530 is low (A10=A11=A12=low);
• /RS is low when A7 is low.
In the replacement circuit the condition is then A6=A7=A10=A11=A12=low
In this respect, gates IC4C and IC4D make no sense (A7 is already low by definition because of its connection to /RS) but does no harm either.
There are three mirrors (at $100-$13F, $200-$23F and $300-$3F) because A9 is don’t care, and the
mirror at $100-$13F is an intended one to create stack space, A8 is don’t care on purpose.
Final conclusion
The replacement circuit does indeed work based on the assumptions about the mask options of the
6530 presented in this document. There is room for improvement, and two superfluous gates can be
removed. Replacing the 74LS02 with a 74LS00 gives an opportunity to incorporate R/W in the
EPROM decode; there are no further gates required, unless A9 is incorporated in the 6532 RAM
address decode. This unfortunately cannot be achieved with the three unused gates in the 74LS00.
A remark
The methodology used in this document can be used to make an educated guess at the mask options of an unknown 6530. One needs to have a schematic diagram of the circuit it is used in, and a dump and/or disassembly of its ROM contents. If the 6530 is still functional, the educated guess can be evaluated further and tested. When all tests are done, a replacement address decoder can be designed and built to drive the control inputs of the replacing 6532. One way of addressing this is to use the basic circuit designed by Ruud Baltissen, and to replace the gates on it with programmable logic (a GAL16V8 for example) to make the circuit universal. With this approach, a dying 6530 is no longer a nightmare, provided its mask options and ROM contents are determined before it ceases to function.