SVG Picture created as 6530-004_dissect_1-6530-004_dissect_1.svg date 2021/11/15 16:28:55 Picture generated by Eeschema-SVG P$3 1P$1 2P$2 3IC2679CMAX4613SO16 O 1I0 2I1 3IC2669A O 1I0 2I1 3IC2670A P$3 1P$1 2P$2 3IC2671CMAX4613SO16 I0 1I1 2O 3IC2672A I0 4I1 5O 6IC2672B I0 1I1 2O 3IC2673A I0 4I1 5O 6IC2673B I1 10O 8I0 9IC2673C O 11I0 12I1 13IC2673D O 1I0 2I1 3IC2674A P$3 1P$1 2P$2 3IC2675CMAX4613SO16 P$3 1P$1 2P$2 3IC2677CMAX4613SO16 P$3 1P$1 2P$2 3IC2678CMAX4613SO16 O 11I0 12I1 13IC2668D P$3 1P$1 2P$2 3IC2680CMAX4613SO16 P$3 1P$1 2P$2 3IC2681CMAX4613SO16 P$3 1P$1 2P$2 3IC2682CMAX4613SO16 P$3 1P$1 2P$2 3IC2683CMAX4613SO16 P$3 1P$1 2P$2 3IC2684CMAX4613SO16 P$3 1P$1 2P$2 3IC2685CMAX4613SO16 P$3 1P$1 2P$2 3IC2686CMAX4613SO16 OE 1I 2O 3IC2687A GND 1 GND OE 1I 2O 3IC2688A GND 1 GND OE 1I 2O 3IC2689A GND 1 GND VCC 1 VCC 1 12 2 R645R-EU_R0603 VCC 1 VCC 1 12 2 R646R-EU_R0603 VCC 1 VCC 1 12 2 R647R-EU_R0603 VCC 1 VCC 1 12 2 R648R-EU_R0603 VCC 1 VCC 1 12 2 R649R-EU_R0603 VCC 1 VCC 1 12 2 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3O 4IC2553B CDQD1C2Q4IC2554A I 3O 4IC2555B CDQD1C2Q4IC2556A CDQD1C2Q4IC2560A I 3O 4IC2561B CDQD1C2Q4IC2562A 1 12 2 R644R-EU_R0603 OE 1I 2O 3IC2567A I 1O 2IC2568A I 1O 2IC2569A OE 4I 5O 6IC2570B GND 1 GND I0 4I1 5O 6IC2574B OE 4I 5O 6IC2575B GND 1 GND I 1O 2IC2576A 1 12 2 R630R-EU_R0603 VCC 1 VCC OE 4I 5O 6IC2577B I 1O 2IC2653A CDQD1C2Q4IC2649A I0 1I1 2O 3IC2606A I0 4I1 5O 6IC2606B I0 1I1 2O 3IC2611A I0 4I1 5O 6IC2611B I1 10O 8I0 9IC2611C O 11I0 12I1 13IC2611D O 1I0 2I1 3IC2614A O 1I0 2I1 3IC2615A P$3 1P$1 2P$2 3IC2616CMAX4613SO16 I 1O 2IC2650A I 1O 2IC2651A I 1O 2IC2652A I0 3I1 4I2 5O 6IC2604B I 1O 2IC2654A I 1O 2IC2655A I 1O 2IC2656A I 1O 2IC2657A P$3 1P$1 2P$2 3IC2658CMAX4613SO16 P$3 1P$1 2P$2 3IC2659CMAX4613SO16 P$3 1P$1 2P$2 3IC2660CMAX4613SO16 P$3 1P$1 2P$2 3IC2661CMAX4613SO16 P$3 1P$1 2P$2 3IC2662CMAX4613SO16 P$3 1P$1 2P$2 3IC2663CMAX4613SO16 P$3 1P$1 2P$2 3IC2664CMAX4613SO16 P$3 1P$1 2P$2 3IC2665CMAX4613SO16 I0 1O 12I2 13I1 2IC2604A CDQD1C2Q4IC2647A CDQD1C2Q4IC2648A I 3O 4IC2603B I 5O 6IC2603C O 8I 9IC2603D I1 10I2 11O 8I0 9IC2604C A1Y510Y411Y312Y213Y114Y015B2C3G2A4G2B5G16Y77Y69IC2618A I 5O 6IC2605C O 8I 9IC2605D O 10I 11IC2605E O 12I 13IC2605F O 4I0 5I1 6IC2619B O 4I0 5I1 6IC2620B O 4I0 5I1 6IC2621B CDQD1C2Q4IC2623A O 4I0 5I1 6IC2622B CDQD1C2Q4IC2646A GND 1 GND I0 1I1 2O 3IC2645A P$3 1P$1 2P$2 3IC2630CMAX4613SO16 P$3 1P$1 2P$2 3IC2629CMAX4613SO16 P$3 1P$1 2P$2 3IC2628CMAX4613SO16 P$3 1P$1 2P$2 3IC2627CMAX4613SO16 CDQD1C2Q4IC2626A CDQD1C2Q4IC2625A CDQD1C2Q4IC2624A VCCGNDVCCGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCC D4R#D2R#D2R#CS1D2R#D5W#D3W#D3W#D4R#D3W#RS0I#D4R#D3W#D3R#RS0I#D4R#D3R#D4W#D3R#D3R#D4W#D4W#D4W#D1R#PB0O#A0IA0ID1W#A0ID1W#D1W#D1W#D1R#D1R#A2I#D2R#A2I#D1R#D2W#D2W#A2I#D2W#A3I#D2W#D2W#A3I#D6R#D6W#D6W#D6W#D6W#D6W#D6R#D6R#D6R#D5R#D7W#D7W#D7W#D7R#D7R#D7R#D7R#PB7O#PA0O#DDRA0DDRA0PB6O#PB6O#PB6IPB6IPB7O#D7R#PB7IPB7ID5W#D5W#D5R#D5R#D5R#D2WB$2B$2B$2D1WD1WD1WD1WD2WB$2D2WD3WD3WD3WD3WD4WD4WD0R#D0W#D0W#D0W#B$3D0W#D0W#D5W#D0R#PA0O#B$3D0R#D0WB$2B$2B$2B$2PB3O#B$1PB2O#PB2O#PB2IA1IA1IPB2IPB3O#PB1IPB3IPB3IPB4O#PB4O#PB4IPB4IPB5O#B$1DDRB0PB0O#DDRB0PB0IB$1B$1PB0IB$1PB5O#B$1PB1O#B$1B$1PB1O#B$1PB1IPA2O#PA4O#PA4O#PA3IPA3IPA3O#PA3O#PA2IPA2IPA4IPA2O#PA1IPA1IPA1O#PA1O#PA0IPA0ID0R#PA4IPA5O#PA5O#PA5IPA5IPA6O#PA6O#PA6IPA6IPA7O#PA7O#PA7IPA7IPB5IPB5ICS1D6WD5WD5WD6WD6WD5WD5WD4WD7WD0WD7WD7WD0W A6iD4r#PA5o#PA5iPA6o#PA6iD6r#D5r#part of 14) IO controlCS1RS0i#A9i#A9iPA4o#A8iA6i#A7iA7i#A8i#CS2PB6PB5ROMRAMIOPA5o#PB2o#PB2iPB1o#PB1iPA1iPA1o#PA2iPA2o#PA3iPA3o#PA4iPA4o#PA5iPA4iPA6iPA6o#PA1o#PA1iD1r#PA2o#PA2iD2r#PA3o#PA3iD3r#PHI1carry#PB5A2i#A2iA3i#A3iA4i#A4iA5i#10) PB6 driver\\buffer1.67kOhmcutA5iA6i#PADcarrycarry#carrycarry#carrycarry#carryIS0like Bit 9like Bit 8like Bit 9like Bit 8PAD20) ROMR_TMRW_TMRA3i#RES74125ROM#RAM#RAM_WA0..5i, A0..5i#A0..9i, A0..9i#D0..7r#D0..7wD0..7r#PB3o#19) RAM64 Bytes1kBD7r#PRE8PRE64W_TMRPB5icarrycarry#Bit 9Bit 8D4w#D3wD3w#D2wD2w#D1wD1w#D0wD0w#D6wD6w#D5wD5w#D4wD4w#D3wD3w#D2wD2w#D1wD1w#RS flipflopIRQPHI2PHI1A1iA0iPA0o#/Q1.67kOhmcutA1i#RS flipflopRSA1iSRQ/QPB5o#W/R#PA0iD0r#74057401DDRA7#DDRA0to CS2 latchD6wD6w#D5wD5w#D4wPB4iIRQ_DISABLER_IRQR_TMRW_TMR16) Timer control18) Timer (down counter)D6r#PB6iPB6o#D5r#PB5iPB5o#D4r#R_IRQPB4o#D3r#PADPB3iPB3o#D2r#PB2iPB2o#D1r#PB1iPB1o#QPHI1A2i#10) PB6 driver\\bufferIO#PHI1A3i#IRQD7r#PHI2PHI1PRE8IS0PRE64PB3iTC#CEN#CEN_T5#741257412574125PRE117) predividerPB4RESR_TMRW_TMRG2BPHI2PHI1TC#CEN#CEN_T5#R_TMRW_TMRPHI1ABCG1G2Amask programmed, The TIM edition.Y0Y1Y2Y374238Y4Y5Y6Y7Timer Interrupt flagCEN#CEN_T5#R_TMRR_DDRAPHI2_inIO#W/R#RESRESRESR_PRAR_PRBW_PRAW_PRBW_DDRBW_DDRAR_DDRBW_TMRPB6PB5PB6PB5PB6PB5PB7iPADPB7PB7o#Note:Unlike in other 65xx peripherals, PA0..7 and PB0..7 inputs are not latched with PHI2=0.Means the CPU reads them directly at the falling edge of PHI2.That's not good for noise immunity of the PA0..7 and PB0..7 inputs.And that's why Bits on the read data bus default to 0.FSTLPADDB7PADDB7A7iA8i#A8iA9i#A9i6) CS1 latchCS1CS27) rwDB7W/R#R/W#PAD8) DB7PHI2_inFSTLD6w#DB7PADD6r#OE_DB#74125D4r#R_IRQA7i#7405D7r#D7w#D0r#D0w#D1r#D1w#D2r#D2w#D3r#D3w#PHI2D4w#D5r#D5w#PADDB7PADDB7PADDB7PADDB7PADPB6iQ1Q1#D0w#D0r#cin#Q0Q074125PB6o#A6i7405to CS1 latch74125cinPADTC#D7r#D6r#D5r#D4r#D3r#D2r#PB6D7wD6w#D5wPHI2like Bit 8like Bit 9like Bit 876543210PHI2PHI1D4w#PHI1PHI2PHI1PRE8PRE64IS0D1wD1r#PHI1PHI2R_TMRW_TMRprescalerunderflowRS flipflopread Interrupt flagNote:Timer runs at full speed after underflow.Writing the timer clears prescale counter.Writing the timer: A0,A1 sets prescaler factor.Reading/writing Timer: A3 enables/disables IRQ.An accidental Timer read during a 6502 RESET sequencecould enable PB7 interrupt generation.FAST#FAST#FAST#Note:for Even Bits, the prescaler factor just masks the counter Bit for the zero detection.for odd Bits, the prescaler factor really clears the counter Bit.latchlatchlatchlatchprescaler factorlatchesPRE174125Timer count enable,low_active.Timer uses carry lookaheadfor the lower 5 Bits.Timer underflowW_TMRPHI1ROM#RAM#ROM#RAM#RAM_WRAM_WPHI1R_PRBD3wD2w#Tcin59) PB7 driver\\buffer01765432R_PRAlike Bit 9W_PRAW_PRBW_DDRBW_DDRAR_DDRBR_DDRARESIRQ_DISABLEPHI2PHI1A3i#IRQ13) some logicA11A1011111000RS0i#3) RS0Note:asynchronous RESET,not synchronizedwith any clock.A12IO#ROM#RESW/R#RAM#OE_DB_RRAM#PHI1RAM_WPHI2R_010R_011W_0101A0transparent latchfully static PHI1PADRS0_inCS1RS0A9A6A8A7CS2W_01111101110XXXXPADY5Y6Y7A0iIO#A1iW/R#A2i#PHI2_inPHI1Note:DB0..7 input buffers sample write data during PHI2_in=1.PRA, DDRA, PRB, DDRB are written during PHI2_in=0....you probably won't expect to see something like that in a 65xx peripheral chip.14) IO controlRESY4RES#2) RESET15) IO logicRS flipflopSRQ/QRS flipflopSRQ/QOE_DB_RW_001W_000R_001R_000R_PRAR_PRBW_PRAW_PRBW_DDRBW_DDRAR_DDRBR_DDRAPHI2_inIOOE_DB#ABCG1G2AG2BY0Y1Y2Y374138PB2PADA3PADA2PADPA6PADPA5PADPA4PADA1PADA4PADPB3PADPA3PADPA2PADPA1PADPA0PAD1.67kOhmDDRA0PA7PB1PB0PAD1.67kOhmDDRB0PB0iPB0o#7412611) PB0 driver\\bufferA9PADA8PADPA0iPADPA7i741257405A7PA7o#1.67kOhmPADA6PADA5PADFSTLA6i#A7iA7i#A8i#CS2CS2#RS0#RS0CS1CS1#CS2CS2#5) A9A8i4) A0NORNORNORROMRAMIOA0iA0i#PADROMRAMA6i#PA0o#74126FSTLFSTL12) PLACS1#RSi0#CS1RS0iA9i#A9iA6iA8iPB4iA7iA7i#A8i#CS2CS2#CS1#RS0i#CS1RS0iA9i#A9iA6iQR_DDRAR_PRAPA7iRESPA7o#W_DDRAW_PRAD7w#D7w/QPHI1D0r#D1r#D2r#RD3r#SRS flipflop/QD4r#D0w#DDRA7#PRA7D6w#D5w#7401D4w#D3w#D2w#D1w#D5r#D7w#D6wD5wD4wD2wD1wD0wD7wD7r#The TIM edition.QRSPHI2PHI1PHI2_inPADRS flipflopPHI2_in1) clock generator0) cheat sheetlogic >concept< only,different from original circuitry6530-004/QQRSRS flipflopDDRB0D6r#D7r#QRSRS flipflop15) IO logicinternal read data bus precharge FETspart of 18) TimerPB4o#D3wDDRA0#74011.67kOhmD0r#PB0iPB0o#D0w#D0w/Q7405W_DDRBW_PRBPB7o#RESPB7iD7w#D7wR_PRBR_DDRBD7r#7401PRB774125DDRB7#part of15) IO logic