Programming Manual - Appendixes

APPENDIX A INSTRUCTION LIST ALPHABETIC BY MNEMONIC DEFINITION OF INSTRUCTION GROUPS A-1

MCS6501-MCS6505 MICROPROCESSOR INSTRUCTION SET - ALPHABETIC SEQUENCE ADC Add Memory to Accumulator with Carry JSR Jump to New Location Saving Return Address AND "AND" Memory with Accumulator ASL Shift Left One Bit (Memory or Accumulator) LDA Load Accumulator with Memory LDX Load Index X with Memory BCC Branch on Carry Clear LDY Load Index Y with Memory BCS Branch on Carry Set LSR Shift Right One Bit (Memory or Accumulator) BEQ Branch on Result Zero BIT Test Bits in Memory with Accumulator NOP No Operation BMI Branch on Result Minus BNE Branch on Result not Zero ORA "OR" Memory with Accumulator BPL Branch on Result Plus PHA Push Accumulator on Stack BRK Force Break PHP Push Processor Status on Stack BVC Branch on Overflow Clear PLA Pull Accumulator from Stack BVS Branch on Overflow Set PLP Pull Processor Status from Stack CLC Clear Carry Flag ROL Rotate One Bit Left (Memory or Accumulator) CLD Clear Decimal Mode ROR Rotate One Bit Right (Memory or Accu) CLI Clear Interrupt Disable Bit RTI Return from Interrupt CLV Clear Overflow Flag RTS Return from Subroutine CMP Compare Memory and Accumulator CPX Compare Memory and Index X SBC Subtract Memory from Accu with Borrow CPY Compare Memory and Index Y SEC Set Carry Flag SED Set Decimal Mode DEC Decrement Memory by One SEI Interrupt Disable Status DEX Decrement Index X by One STA Store Accumulator in Memory DEY Decrement Index Y by One STX Store Index X in Memory STY Store Index Y in Memory EOR "Exclusive Or" Memory with Accumulator TAX Transfer Accumulator to Index X INC Increment Memory by One TAY Transfer Accumulator to Index Y INX Increment Index X by One TSX Transfer Stack Pointer to Index X INY Increment Index Y by One TXA Transfer Index X to Accumulator TXS Transfer Index X to Stack Pointer JMP Jump to New Location TYA Transfer Index Y to Accumulator

A-2

A.1 INTRODUCTION The microprocessor instruction set is divided into three basic groups. The first group has the greatest addressing flexibility and consists of the most general purpose instructions such as Load, Add, Store, etc. The second group includes the Read, Modify, Write instructions such as Shift, Increment, Decrement and the Register X movement instructions. The third group contains all the remaining instructions, including all stack operations, the register T, compares for X and Y and instructions which do not fit naturally into Group One or Group Two. There are eight Group One instructions, eight Group Two instructions, and all of the 39 remaining instructions are Group Three instructions. The three groups are obtained by organizing the OP CODE pattern to give maximum addressing flexibility (16 addressing combinations) to Group One,to give eight combinations to Group Two instructions and the Group Three instructions are basically individually decoded. A.2 GROUP ONE INSTRUCTIONS These instructions are: Add With Carry (ADC), (AND), Compare (CMP), Exclusive Or (EOR), Load A (LDA), Or (ORA), Subtract With Carry (SBC), and Store A (STA). Each of these instructions has a potential for 16 addressing modes. However, in the MCS6501 through MCS6505, only eight of the available modes have been used. Addressing modes for Group One are: Immediate, Zero Page, Zero Page Indexed by X, Absolute, Absolute Indexed by X, Absolute Indexed by Y, Indexed Indirect, Indirect Indexed. The unused eight addressing modes are to be used in future versions of the MCS650X product family to allow addressing of additional on-chip registers, of on-chip I/O ports, and to allow two byte word processing.

A-3

A.3 GROUP TWO INSTRUCTIONS Group Two instructions are primarily Read, Modify, Write instructions. There are really two subcategories within the Group Two instructions. The components of the first group are shift and rotate instructions and are: Shift Right (LSR), Shift Left (ASL), Rotate Left (ROL), and Rotate Right (ROR). The second subgroup includes the Increment (INC) and Decrement (DEC) instructions and the two index register X instructions, Load X (LDX) and Store X (STX). These instructions would normally have eight addressing modes available to them because of the bit pattern. However, to allow for upward expansion, only the following addressing modes have been de- fined: Zero Page, Zero Page Indexed by X, Absolute, Absolute Indexed by X, and a special Accumulator (or Register) mode. The four shift in- structions all have register A operations; the incremented or decremented Load X and Store X instructions also have accumulator modes although the Increment and Decrement Accumulator has been reserved for other purposes. Load X from A has been assigned its own mnemonic, TAX. Also included in this group are the special functions of Decrement X which is one of the special cases of Store X. Included also in this group in the X decodes are the TXS and TSX instructions. All Group One instructions have all addressing modes available to each instruction. In the case of Group Two instructions, another address- ing mode has been added; that of the accumulator and the other special de- codes have also been implemented in this basic group. However, the primary function of Group Two instructions is to perform some memory operation using the appropriate index. It should be noted for documentation purposes that the X instructions have a special mode of addressing in which register Y is used for all in- dexing operations; thus, instead of Zero Page Indexed by X, X instructions have Zero Page Indexed by Y, and instead of having Absolute Indexed by X, X instructions have Absolute Indexed by Y.

A-4

A.4 GROUP THREE INSTRUCTIONS There are really two major classifications of Group Three in- structions; the modify Y register instructions, Load Y (LDY), Store Y (STY), Compare Y (CPY), and Compare X (CPX), instructions actually occupy about half of the OP CODE space for the Group Three instructions. Increment X (INX) and Increment Y (INY) are special subsets of the Compare X and Compare Y instructions and all of the branch instructions are in the Group Three instructions. Instructions in this group consist of all of the branches: BCC, BCS, BEQ, BMI, BNE, BPL, BPC and BPS. All of the flag operations are also de- voted to one addressing mode; they are: CLC, SEC, CLD, SED, CLI, SEI and CLV. All of the push and pull instructions and stack operation instructions are Group Three instructions. These include: BRK, JSR, PHA, PHP, PLA and PLP. The JMP and BIT instructions are also included in this group. There is no common addressing mode available to members of this group. Load Y, Store Y, BIT, Compare X and Compare Y have Zero Page and Absolute, and all of the Y and X instructions allow Zero Page Indexed operations and Immediate.

A-5

APPENDIX B INSTRUCTION LIST ALPHABETIC BY MNEMONIC WITH OP CODES, EXECUTION CYCLES AND MEMORY REQUIREMENTS B-1

The following notation applies to this summary: A Accumulator X, Y Index Registers M Memory P Processor Status Register S Stack Pointer x Change - No Change + Add ^ Logical AND - Subtract v Logical Exclusive Or ^ Transfer from Stack v Transfer to Stack -> Transfer to <- Transfer to V Logical OR PC Program Counter PCH Program Counter High PCL Program Counter Low OPER OPERAND # IMMEDIATE ADDRESSING MODE Note: At the top of each table is located in parentheses a reference number (Ref: xx) which directs the user to that Section in the MCS6500 Microcomputer Family Programming Manual in which the instruction is defined and discussed.

B-2

ADC

ADC Add memory to accumulator with carry

ADC

Operation: A + M + C -> A, C

(Ref: 2.2.1)

N	Z	C	I	D	V
x	x	x	-	-	x

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Immediate Zero Page Zero Page, X Absolute Absolute, X Absolute, Y (Indirect, X) (Indirect), Y	ADC #Oper ADC Oper ADC Oper, X ADC Oper ADC Oper, X ADC Oper, Y ADC (Oper, X) ADC (Oper), Y	69 65 75 6D 7D 79 61 71	2 2 2 3 3 3 2 2	2 3 4 4 4* 4* 6 5*

* Add 1 if page boundary is crossed.

AND

AND Memory with Accumulator)

AND

Operation: A ^ M -> A

(Ref: 2.2.3.0)

N	Z	C	I	D	V
x	x	-	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Immediate Zero Page Zero Page, X Absolute Absolute, X Absolute, Y (Indirect, X) (Indirect), Y	AND # Oper AND Oper AND Oper, X AND Oper AND Oper, X AND Oper, Y AND (Oper, X) AND (Oper), Y	29 25 35 2D 3D 39 21 31	2 2 2 3 3 3 2 2	2 3 4 4 4* 4* 6 5

* Add 1 if page boundary is crossed.

ASL

ASL Shift Left One Bit (Memory or Accumulator)

ASL

Operation: C <- 7 6 5 4 3 2 1 0 <- 0

(Ref: 10.2)

N	Z	C	I	D	V
x	x	x	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Accumulator Zero Page Zero Page, X Absolute Absolute, X	ASL A ASL Oper ASL Oper, X ASL Oper ASL Oper, X	0A 06 16 0E 1E	1 2 2 3 3	2 5 6 6 7

BCC

BCC Branch on Carry Clear

BCC

Operation: Branch on C = 0

(Ref: 4.1.1.3)

N	Z	C	I	D	V
-	-	-	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Relative	BCC Oper	90	2	2*

* Add 1 if branch occurs to same page.
* Add 2 if branch occurs to same page.

BCS

BCS Branch on Carry Set

BCS

Operation: Branch on C = 1

(Ref: 4.1.1.4)

N	Z	C	I	D	V
-	-	-	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Relative	BCS Oper	B0	2	2*

* Add 1 if branch occurs to same page.
* Add 2 if branch occurs to same page.

BEQ

BEQ Branch on Result Zero

BEQ

Operation: Branch on Z = 1

(Ref: 4.1.1.5)

N	Z	C	I	D	V
-	-	-	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Relative	BEQ Oper	F0	2	2*

* Add 1 if branch occurs to same page.
* Add 2 if branch occurs to same page.

BIT

BIT Test bits in memory with accumulator

BIT

Operation: a ^ M, M7 -> N, M6 ->V

(Ref: 4.2.1.1)

N	Z	C	I	D	V
M7	X	-	-	-	M6

Bit 6 and bit 7 are transferred to the status register.
If the result of A ^ M is zero then Z = 1, otherwise Z = 0

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Zero Page Absolute	BIT Oper BIT Oper	24 2C	2 3	3 4

BMI

BMI Branch on result minus

BMI

Operation: Branch on N = 1

(Ref: 4.1.1.1)

N	Z	C	I	D	V
-	-	-	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Relative	BMI Oper	30	2	2*

* Add 1 if branch occurs to same page.
* Add 2 if branch occurs to same page.

BNE

BNE Branch on result not zero

BNE

Operation: Branch on Z = 0

(Ref: 4.1.1.6)

N	Z	C	I	D	V
-	-	-	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Relative	BNE Oper	D0	2	2*

* Add 1 if branch occurs to same page.
* Add 2 if branch occurs to same page.

BPL

BPL Branch on result plus

BPL

Operation: Branch on N = 0

(Ref: 4.1.1.2)

N	Z	C	I	D	V
-	-	-	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Relative	BPL Oper	10	2	2*

* Add 1 if branch occurs to same page.
* Add 2 if branch occurs to same page.

BRK

BRK Force Break

BRK

Operation: Forced Interrupt PC + 2 v P v

(Ref: 9.11)

N	Z	C	I	D	V
-	-	-	1	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Implied	BRK	00	1	7

1. A BRK command cannot be masked by setting I.

BVC

BVC Branch on overflow clear

BVC

Operation: Branch on V = 0

(Ref: 4.1.1.8)

N	Z	C	I	D	V
-	-	-	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Relative	BVC Oper	50	2	2*

* Add 1 if branch occurs to same page.
* Add 2 if branch occurs to same page.

BVS

BVS Branch on overflow set

BVS

Operation: Branch on V = 1

(Ref: 4.1.1.7)

N	Z	C	I	D	V
-	-	-	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Relative	BVS Oper	70	2	2*

* Add 1 if branch occurs to same page.
* Add 2 if branch occurs to same page.

CLC

CLC Clear carry flag

CLC

Operation: 0 -> C

(Ref: 3.0.2)

N	Z	C	I	D	V
-	-	0	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Implied	CLC	18	1	2

CLD

CLD Clear decimal mode

CLD

Operation: 0 -> D

(Ref: 3.3.2)

N	Z	C	I	D	V
-	-	-	-	0	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Implied	CLD	D8	1	2

CLI

CLI Clear interrupt disable bit

CLI

Operation: 0 -> I

(Ref: 3.2.2)

N	Z	C	I	D	V
-	-	-	0	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Implied	CLI	58	1	2

CLV

CLV Clear overflow flag

CLV

Operation: 0 -> V

(Ref: 3.6.1)

N	Z	C	I	D	V
-	-	-	-	-	0

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Implied	CLV	B8	1	2

CMP

CMP Compare memory and accumulator

CMP

Operation: A - M

(Ref: 4.2.1)

N	Z	C	I	D	V
x	x	x	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Immediate Zero Page Zero Page, X Absolute Absolute, X> Absolute, Y (Indirect,X) (Indirect), Y	CMP #Oper CMP Oper CMP Oper, X CMP Oper CMP Oper, X CMP Oper, Y CMP (Oper, X) CMP (Oper), Y	C9 C5 D5 CD DD D9 C1 D1	2 2 2 3 3 3 2 2	2 3 4 4 4* 4* 6 5*

* Add 1 if page boundary is crossed.

CPX

CPX Compare Memory and Index X

CPX

Operation: X - M

(Ref: 7.8)

N	Z	C	I	D	V
x	x	x	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Immediate Zero Page Absolute	CPX #Oper CPX Oper CPX Oper	E0 E4 EC	2 2 3	2 3 4

CPY

CPY Compare Memory and Index Y

CPY

Operation: Y - M

(Ref: 7.9)

N	Z	C	I	D	V
x	x	x	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Immediate Zero Page Absolute	CPY #Oper CPY Oper CPY Oper	C0 C4 CC	2 2 3	2 3 4

DEC

DEC Decrement memory by one

DEC

Operation: M - 1 -> M

(Ref: 10.7)

N	Z	C	I	D	V
x	x	-	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Zero Page Zero Page, X Absolute Absolute, X	DEC Oper DEC Oper, X DEC Oper	C6 D6 CE DE	2 2 3 3	5 6 6 7

DEX

DEX Decrement index X by one

DEX

Operation: X - 1 -> X

(Ref: 7.6)

N	Z	C	I	D	V
x	x	-	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Implied	DEX	CA	1	2

DEY

DEY Decrement index Y by one

DEY

Operation: Y - 1 -> Y

(Ref: 7.7)

N	Z	C	I	D	V
x	x	-	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Implied	DEY	88	1	2

EOR

EOR "Exclusive-Or" memory with accumulator

EOR

Operation: A v M -> A

(Ref: 2.2.3.2)

N	Z	C	I	D	V
x	x	-	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Immediate Zero Page Zero Page, X Absolute Absolute, X Absolute, Y (Indirect, X) (Indirect), Y	EOR # Oper EOR Oper EOR Oper, X EOR Oper EOR Oper, X EOR Oper, Y EOR (Oper, X) EOR (Oper), Y	49 45 55 4D 5D 59 41 51	2 2 2 3 3 3 2 2	2 3 4 4 4* 4* 6 5*

* Add 1 if page boundary is crossed

INC

INC Increment memory by one

INC

Operation: M + -> M

(Ref: 10.6)

N	Z	C	I	D	V
x	x	-	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Zero Page Zero Page, X Absolute Absolute, X	INC Oper INC Oper, X INC Oper INC Oper, X	E6 F6 EE FE	2 2 3 3	5 6 6 7

INX

INX Increment Index X by one

INX

Operation: X + -> X

(Ref: 7.4)

N	Z	C	I	D	V
x	x	-	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Implied	INX	E8	1	2

INY

INY Increment Index Y by one

INY

Operation: Y + -> Y

(Ref: 7.5)

N	Z	C	I	D	V
x	x	-	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Implied	INY	C8	1	2

JMP

JMP Jump to new location

JMP

Operation: (PC + 1) -> PCL
(PC + 1) -> PCH

(Ref: 4.0.2)
(Ref: 9.8.1)

N	Z	C	I	D	V
-	-	-	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Absolute Indirect	JMP Oper JMP (Oper)	4C 6C	3 3	3 5

JSR

JSR Jump to new location saving return address

JSR

Operation: PC + 2 v , (PC + 1) -> PCL
(PC + 1) -> PCH

(Ref: 8.1)

N	Z	C	I	D	V
-	-	-	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Absolute	JSR Oper	20	3	6

LDA

LDA Load accumulator with memory

LDA

Operation: M -> A

(Ref: 2.1.1)

N	Z	C	I	D	V
x	x	-	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Immediate Zero Page Zero Page, X Absolute Absolute, X Absolute, Y (Indirect, X) (Indirect), Y	LDA #Oper LDA Oper LDA Oper, X LDA Oper LDA Oper, X LDA Oper, Y LDA (Oper, X) LDA (Oper), Y	A9 A5 B5 AD BD B9 A1 B1	2 2 2 3 3 3 2 2	2 3 4 4 4* 4* 6 5*

* Add 1 if page boundary is crossed

LDX

LDX Load index X with memory

LDX

Operation: M -> X

(Ref: 7.0)

N	Z	C	I	D	V
x	x	-	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Immediate Zero Page Zero Page, Y Absolute Absolute, Y	LDX #Oper LDX Oper LDX Oper, Y LDX Oper LDX Oper, Y	A2 A6 B6 AE BE	2 2 2 3 3	2 3 4 4 4*

* Add 1 if page boundary is crossed

LDY

LDY Load index Y with memory

LDY

Operation: M -> Y

(Ref: 7.1)

N	Z	C	I	D	V
x	x	-	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Immediate Zero Page Zero Page, X Absolute Absolute, X	LDY #Oper LDY Oper LDY Oper, X LDY Oper LDY Oper, X	A0 A4 B4 AC BC	2 2 2 3 3	2 3 4 4 4*

* Add 1 if page boundary is crossed

LSR

LSR Shift right one bit (memory or accumulator)

LSR

Operation: 0 -> byte ->C

(Ref: 10.1)

N	Z	C	I	D	V
0	x	x	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Accumulator Zero Page Zero Page, X Absolute Absolute, X	LSR A LSR Oper LSR Oper, X LSR Oper LSR Oper, X	4A 46 56 4E 5E	1 2 2 3 3	2 5 6 6 7

NOP

NOP No operation

NOP

Operation: No Operation (2 cycles)

N	Z	C	I	D	V
-	-	-	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Implied	NOP	EA	1	2

ORA

ORA "OR" memory with accumulator

ORA

Operation: A v M -> A

(Ref: 2.2.3.1)

N	Z	C	I	D	V
x	x	-	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Immediate Zero Page Zero Page, X Absolute Absolute, X Absolute, Y (Indirect, X) (Indirect), Y	ORA #Oper ORA Oper ORA Oper, X ORA Oper ORA Oper, X ORA Oper, Y ORA (Oper, X) ORA (Oper), Y	09 05 15 0D 1D 19 01 11	2 2 2 3 3 3 2 2	2 3 4 4 4* 4* 6 5

* Add 1 on page crossing

PHA

PHA Push accumulator on stack

PHA

Operation: A v

(Ref: 8.5)

N	Z	C	I	D	V
-	-	-	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Implied	PHA	48	1	3

PHP

PHP Push processor status on stack

PHP

Operation: P v

(Ref: 8.11)

N	Z	C	I	D	V
-	-	-	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Implied	PHP	08	1	3

PLA

PLA Pull accumulator from stack

PLA

Operation: A ^

(Ref: 8.6)

N	Z	C	I	D	V
x	x	-	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Implied	PLA	68	1	4

PLP

PLP Pull processor status from stack

PLP

Operation: P ^

(Ref: 8.12)

From Stack

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Implied	PLP	28	1	4

ROL

ROL Rotate one bit left (memory or accumulator)

ROL

Operation: |-<- byte <- C <-|

(Ref: 10.3)

N	Z	C	I	D	V
x	x	x	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Accumulator Zero Page Zero Page, X Absolute Absolute, X	ROL A ROL Oper ROL Oper, X ROL Oper ROL Oper, X	2A 26 36 2E 3E	1 2 2 3 3	2 5 6 6 7

ROR

ROR Rotate one bit right (memory or accumulator)

ROR

Operation: |-> C -> byte ->-|

(Ref: 10.4)

N	Z	C	I	D	V
x	x	x	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Accumulator Zero Page Zero Page, X Absolute Absolute, X	ROR A ROR Oper ROR Oper, X ROR Oper ROR Oper, X	2A 26 36 2E 3E	1 2 2 3 3	2 5 6 6 7

Note: ROR instruction will be available on MCS650X microprocessors after June, 1976.

RTI

RTI Return from interrupt

RTI

Operation: P ^ PC^

(Ref: 9.6)

From Stack

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Implied	RTI	40	1	6

RTS

RTS Return from subroutine

RTS

Operation: PC^, PC + 1 -> PC

(Ref: 8.2)

N	Z	C	I	D	V
-	-	-	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Implied	RTS	60	1	6

SBC

SBC Subtract memory from accumulator with borrow

SBC

Operation: A - M - -C -> A
Note: -C = Borrow

(Ref: 2.2.2)

N	Z	C	I	D	V
x	x	x	-	-	x

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Immediate Zero Page Zero Page, X> Absolute Absolute, X Absolute, Y (Indirect, X) (Indirect), Y	SBC #Oper SBC Oper SBC Oper, X SBC Oper SBC Oper, X SBC Oper, Y SBC (Oper, X) SBC (Oper), Y	E9 E5 F5 ED FD F9 E1 F1	2 2 2 3 3 3 2 2	2 3 4 4 4* 4* 6 5*

* Add 1 when page boundary is crossed.

SEC

SEC Set carry flag

SEC

Operation: 1 -> C

(Ref: 3.0.1)

N	Z	C	I	D	V
-	-	1	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Implied	SEC	38	1	2

SED

SED Set decimal mode

SED

Operation: 1 -> D

(Ref: 3.3.1)

N	Z	C	I	D	V
-	-	-	-	1	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Implied	SED	F8	1	2

SEI

SEI Set interrupt disable status

SEI

Operation: 1 -> I

(Ref: 3.2.1)

N	Z	C	I	D	V
-	-	-	1	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Implied	SEI	78	1	2

STA

STA Store accumulator in memory

STA

Operation: A -> M

(Ref: 2.1.2)

N	Z	C	I	D	V
-	-	-	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Zero Page Zero Page, X Absolute Absolute, X Absolute, Y (Indirect, X) (Indirect), Y	STA Oper STA Oper, X STA Oper STA Oper, X STA Oper, Y STA (Oper, X) STA (Oper), Y	85 95 8D 9D 99 81 91	2 2 3 3 3 2 2	3 4 4 5 5 6 6

STX

STX Store index X in memory

STX

Operation: X -> M

(Ref: 7.2)

N	Z	C	I	D	V
-	-	-	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Zero Page Zero Page, Y Absolute	STX Oper STX Oper, Y STX Oper	86 96 8E	2 2 3	3 4 4

STY

STY Store index Y in memory

STY

Operation: Y -> M

(Ref: 7.3)

N	Z	C	I	D	V
-	-	-	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Zero Page Zero Page, X Absolute	STY Oper STY Oper, X STY Oper	84 94 8C	2 2 3	3 4 4

TAX

TAX Transfer accumulator to index X

TAX

Operation: A -> X

(Ref: 7.11)

N	Z	C	I	D	V
x	x	-	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Implied	TAX	AA	1	2

TAY

TAY Transfer accumulator to index Y

TAY

Operation: A -> Y

(Ref: 7.13)

N	Z	C	I	D	V
x	x	-	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Implied	TAY	A8	1	2

TYA

TYA Transfer index Y to accumulator

TYA

Operation: Y -> A

(Ref: 7.14)

N	Z	C	I	D	V
x	x	-	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Implied	TYA	98	1	2

TSX

TSX Transfer stack pointer to index X

TSX

Operation: S -> X

(Ref: 8.9)

N	Z	C	I	D	V
x	x	-	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Implied	TSX	BA	1	2

TXA

TXA Transfer index X to accumulator

TXA

Operation: X -> A

(Ref: 7.12)

N	Z	C	I	D	V
x	x	-	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Implied	TXA	8A	1	2

TXS

TXS Transfer index X to stack pointer

TXS

Operation: X -> S

(Ref: 8.8)

N	Z	C	I	D	V
-	-	-	-	-	-

Addressing Mode	Assembly Language Form	OP Code	No. Bytes	No. Cycles
Implied	TXS	9A	1	2

APPENDIX C INSTRUCTION ADDRESSING MODES AND RELATED EXECUTION TIMES C-1

C-2










APPENDIX D


OPERATION INSTRUCTION LISTING



HEXADECIMAL SEQUENCE













D-1

APPENDIX E SUMMARY OF ADDRESSING MODES E-1

This appendix is to serve the user in providing a reference for the MCS650X addressing modes. Each mode of address is shown with a symbolic illustration of the bus Status at each cycle during the instruction fetch and execution. The example number as found in the text is provided for reference purposes. E.l IMPLIED ADDRESSING Example 5.3: Illustration of implied addressing Clock Cycle Address Bus Program Counter Data Bus Comments 1 PC PC + 1 OP CODE Fetch OP CODE 2 PC + 1 PC + I New Ignore New OP CODE OP CODE; Decode Old OP CODE 3 PC + 1 PC + 2 New Fetch New OP CODE OP CODE; Execute Old OP CODE

E-2

E. 2 IMMEDIATE ADDRESSING Example 5.4: Illustration of immediate addressing Clock Cycle Address Bus Program Counter Data Bus Comments 1 PC PC + 1 OP CODE Fetch OP CODE 2 PC + 1 PC + 2 Data Fetch Data, Decode OP CODE 3 PC + 2 PC + 3 New Fetch New OP CODE OP CODE, Execute Old OP CODE E.3 ABSOLUTE ADDRESSING Example 5.5: Illustration of absolute addressing Clock Cycle Address Bus Program Counter Data Bus Comments 1 PC PC + 1 OP CODE Fetch OP CODE 2 PC + 1 PC + 2 ADL Fetch AOL, Decode OP CODE 3 PC + 2 PC + 3 ADH Fetch AOH, Retail AOL 4 AOH, AOL PC + 3 Data Fetch Data 5 PC + 3 PC + 4 New Fetch New OP CODE OP CODE, Execute Old OP CODE

E-3

E.4 ZERO PAGE ADDRESSING Example 5.6: Illustration of zero page addressing Clock Cycle Address Bus Program Counter Data Bus Comments 1 PC PC + 1 OP CODE Fetch OP CODE 2 PC + 1 PC + 2 ADL Fetch ADL, De- code OP CODE 3 00, AOL PC + 2 Data Fetch Data 4 PC + 2 PC + 3 New Fetch New OP CODE OP CODE, Exe- cute Old OP CODE E.5 RELATIVE ADDRESSING - (Branch Positive, no crossing of page boundaries) Example 5.8: Illustration of relative addressing--branch positive taken, no crossing of page boundaries External Internal Cycle Address Bus Data Bus Operation Operation 1 0100 OP CODE Fetch Finish Previous Oper- OP CODE ation, Increment Pro- gram Counter to 101 2 0101 +50 Fetch Interpret Instruction, Offset Increment Progran Counter to 102 3 0102 Next Fetch Next Check Flags, Add Rela- OP CODE OP CODE tive to PCL, Increment Program Counter to 103 4 0152 Next Fetch Next Transfer Results to OP CODE OP CODE PCL, Increment Program Counter to 153

E-4

E.6 ABSOLUTE INDEXED ADDRESSING - (with page crossing) Step 5 is deleted and the data in step 4 is valid when no page crossing occurs. Example 6.7: Absolute Indexed; With Page Crossing Address Data External Internal Cycle Bus Bus Operation Operation 1 0100 OP CODE Fetch OP CODE Finish Previous Operation Increment PC to 101 2 0101 BAL Fetch BAL Interpret Instruction Increment PC to 102 3 0102 BAB Fetch BAH Add BAL + Index Increment PC to 103 4 BAH,BAL Data Fetch Data Add BAH + Carry +X (Ignore) (Data is ignored) 5 BAH+1, Data Fetch Data BAL+X 6 0103 Next OP Fetch Next Finish Operation CODE OP CODE

E-5

E.7 ZERO PAGE INDEXED ADDRESSING Example 6.8: Illustration of Zero Page Indexing Address Data External Internal Cycle Bus Bus Operation Operation 1 0100 OP CODE Fetch OP CODE Finish Previous Operation 2 0101 BAL Fetch Base Interpret Instruct- Address Low ion (BAL) 3 D0,BAL Data Fetch Add: BAL + X (Dis- Discarded carded Data 4 00,BAL Data Fetch Data 5 0102 Next OP Fetch Next OP Finish Operation CODE CODE

E-6

E.8 INDEXED INDIRECT ADDRESSING Example 6.10: Illustration of Indexed Indirect Addressing Address Data External Internal Cycle Bus Bus Operation Operation 1 0100 OP CODE Fetch OP CODE Finish Previous Operation 2 0101 BAL Fetch BAL Interpret In- struction 3 00,BAL DATA (Dis- Fetch Discard- Add BAL + X carded) ed DATA 4 00,BAL AOL Fetch ADL Add 1 to BAL + X 5 00,BAL Fetch ADH Hold ADL + x + l 6 ADH,ADL DATA Fetch DATA 7 0102 Next OP Fetch Next OP Finish Operation CODE

E-7

E.9 INDIRECT IVDEXED ADDRESSING (with page crossing) Step 6 is deleted and the data in step 5 is valid when no page crossing occurs. Example 6.12: Indirect Indexed Addressing (With Page Crossing) Address Data External Internal Cycle Bus Bus Operation Operation 1 0100 OP CODE Load OP CODE Finish Previous Operation 2 0101 IAL Fetch IAL Interpret In- struction 3 00,IAL BAL Fetch BAL Add 1 to IAL 4 00,IAL BAH Fetch BAH Add BAL to Y +1 5 BAH,BAL DATA(Dis- Fetch DATA Add 1 to BAH + Y carded) (Discarded) 6 BAH + 1 DATA Fetch Data BAL + Y 7 0102 Next OP Fetch Next OP Finish This CODE CODE Operation

E-8

APPENDIX F MCS650X PROGRAMMING MODEL F-1

F-2

APPENDIX G DISCUSSION - INDIRECT ADDRESSING G-1

The MCS650X microprocessors have a special form of addressing known as Indirect. The writeup on Indirect addressing describes the basic operation of Indirect. It is the intent of this discussion to acquaint the user with some of the uses and applications of Indirect addressing. The Indirect address is really an address that would have been coded in line as in the case of Absolute except for the fact that the address is not known at the time the user writes the program. As has been in- dicated several times in the basic body of the documentation, it is sig- nificantly more efficient with the organization of the MGS65OX to assign addresses and implement them if the addressing structure is known. How- ever, that is not always possible to do. For instance, in order to mini- mize the coding of a subroutine or general purpose Set of coding, it is often desirable to work with a range of addressing that is not possible to cover in a normal index, or in the case of subroutine where it is neces- sary for the addresses to be variable depending on which part of the whole program called the address. It is probably this discussion which best amplifies the need for calculated addresses. It should be fairly obvious to the user that a general purpose subroutine cannot contain the address of the operations. Therefore, instead of having the instruction LDA followed by the value that the programmer wants to load, in a subroutine it may be desirable to do a Load A from a calculated or specified address. The use of the Indirect Addressing Mode is to give the user a loca- tion in Page Zero in which can be put the calculated address. Then the subroutine instruction can call this calculated address using the form Load A from an address pointed to by the next byte in program sequence. The word "indirect" technically comes from the fact that instead of taking the address which is immediately following the instruction, the next value in program sequence is a pointer to the address. The Indirect pointer will be referred to from now on as IAL, because it is a Zero Page address and, therefore, is a low order byte. The in- direct instructions are written in the form "Load A" followed by IAL.

G-2

IAL points to an address which had been previously stored into Page Zero. This gives the user the flexibility of addressing anywhere in memory with a calculated address. However, the real value of Indirect is not in just having Indirect but having the ability to have Indirect modified. This is the reason for which indirect indexed instruction is implemented rather than straight indirect. An example of the indirect indexed in sub- routining is covered in Section 6.5, but it should be noted that the in- direct indexed instruction should be used whenever the user does not know the exact address at tine of compilation. Although there nay be other in- teresting and esoteric uses of the indirect index instruction, this is the most common one. The second form of indirect is very powerful for certain types of applications. Chapter 11 shows the use of tables which have pointers and the advantage of running down one table of pointers until a match is found and then using the same index to address a second table to perform an opera- tion. This is the classical stack processor type of architecture but it requires a special discipline at the tine a program is originally defined. Both the indirects require a concept of memory management that is not obvious to the novice programmer. The concept of indexed indirect is that memory has to be viewed as a series of tables, in which access to one set of tables is accomplished by indexing through a list of pointers. One set of tables might be searched to perform some type of testing or operation. Then the sane index is then used to process another set of pointers. This concept is only applicable to operations in which a variety of inputs are being serviced. A classical application is when several remote devices are being managed by the same control program. An example might be having three teletypes tied on to a device, each teletype is being manually controlled and can be under con- trol of the user program. In this type of message handling environment, the control program for the teletypes does nothing more than collect strings of data from the input device and then performs operations on the string

G-3

upon seeing a control signal, usually a carriage return in this case of the teletype. Because any one of the teletypes can he causing any one of the series of operations, this program does not lend itself well to the concept of absolute addressing. In fact, most of the subroutines which deal with the individual processing should be written address independent. This normally allows the addition of more devices without paying any penal- ty in terms of programming. Therefore, this is a subroutine or nonabsolute type of operation in which the indirect indexed would not apply because each of the various operations use a function of position. In other words, one can assign a series of tables that point at the teletype itself; an- other set that points at an outgoing message stream and another set that points to a series of tables which keep the Status of the device. Each of these pointers is considered to be an individual address at the be- ginning of a string. Each string is a variable length. The teletype strings may consist of a three character message followed by a character return or a 40 character message followed by a character return. In the MCS650x, this system will be implemented by means of developing a series of indirect pointers. Each teletype will have an indirect pointer. Its I/O port has another indirect pointer that points at the put-away string, another one that points at the teletype message output string, another one that points at its status table. If all of the teletypes work this way, it can be seen that the coding to put data into the input message table is the same for all the teletypes and is totally independent of the teletype in which data is being stored. The index register X serves as a control for the tables so that if all tables were sequentially organized, X would point at the proper value for each operation. A s4mple operation might be: read teletype three, trans- fer the data to teletype three input register, update teletype three counter, check to see that teletype three is still active, and decide whether or not to return to signal teletype three back. The coding to perform each of these operations would be exactly the same as coding for teletype two, if the tables were organized such that X was an index register for the pointers. This is the type of string manipulation application for which indexed

G-4

indirect was designed and only when a program can be organized for this technique is the indirect used to its maximum potential. The advantages for organizing for this type of approach when the problem requires string manipulation is significant; the comprehensive I/O program is roughly one half the memory and one fourth the execution time of several other microprocessors which do not have this indexed indirect feature.

G-5

APPENDIX H REVIEW OF BINARY AND BINARY CODED DECIMAL ARITHMETIC H-1

The number 1789 is assumed by most people to mean one thousand, seven hundred eighty-nine, or 1 x 10³ + 7 x 10² + 8 x 10¹ + 9 x 10⁰. However, until the number base is defined, it might mean l x 16³ + 7 x 16² + 8 x 16¹ + 9 x 16⁰ which is hexadecimal and the form used in the microprocessor. In order to distinguish between numbers on different bases, mathema- ticians usually write 1789₁₀ or just 1789 for base 10, or decimal, and l789₁₆ for base 16 for hexadecimal. Because very few computers or I/O de- vices allow subscripting, all hexadecimal numbers are preceded by a $ notation. Then 1789 means base 10 and $1789 means base 16. Why hexadeci- mal? This is a convenient way of representing 2 digits in 8 bits. The MCS650X is a byte-oriented microprocessor which means most opera- tions have 8-bit operations. There are 2 ways to look at 8 bits. The first is as 8 individual bits in which 00001000 means that bit 3 (bit 7 to 0 representation) is on and all other bits are off or as an 8-bit binary number in which case the value is 0x 2⁷ + 0 x 2⁶ + 0 x 2⁵ + 0 x 2⁴ + l x 2³ + 0 x 2² + 0 x 2¹ + 0 x 2⁰ = 8 or $08. For logic analysis purposes, each bit is unique, but for arithmetic purposes, the 8 bits are treated as a binary number.

H-2

Binary Arithmetic Rules: 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 0 with a carry Carry occurs when the resulting number is too long for the base. In decimal, 8 + 4 = 2 + 10. In hexadecimal, $8 + $4 = $C (see hexadecimal details), so that 8 + 4 has a carry in base 10 but not in base 16. Using these rules to add 8 + 2 in binary gives the following: 00001000 8 1 x 2³ 00000010 +2 1 x 2¹ 00001010 10 1 x 2³ + 1 x 2¹ Therefore, any number from 0 - 255 may be represented in 8 bits, and binary addition performed using the basic binary add equation, Rj = (A_j v B_j v C_j-1), where, as defined previously, V is notation for Exclusive-Or. In most applications, it is also necessary to subtract. Subtract operations either require a different hardware implementation or a new way representing numbers. A combination of this is to implement a simple inverter in each bit. This would make 00001100 12 11110011 -12 However, when subtracting 12 from 12, the result should also be 0. 00001100 +12 11110011 -12 11111111 0 However, if a carry is added to the complemented number: 1 Carry 00001100 12 11110011 -12 00000000 = 0 If, instead of representing -12 as the complement of 12, it is represented as the complement plus carry, the following is obtained:

H-3

11110011 = 12 1 = Carry 11110100 = -12 00001100 +12 00000000 = 0 This representation is called two's complement and represents the way that negative numbers are kept in the microcomputer. Below are examples of negative numbers represented in two's complement form. -0 = 00000000 -1 = 11111111 -2 = 11111110 -3 = 11111101 -4 = 11111100 -5 = 11111011 -6 = 11111010 -7 = 11111001 -8 = 11111000 -9 = 11110111 Hexadecimal is the representation of numbers to the base 16. The fol- lowing table shows the advantages of Hex: Hexadecimal Binary Decimal 0 0000 00 1 0001 01 2 0010 02 3 0011 03 4 0100 04 5 0101 05 6 0110 06 7 0111 07 B 1000 08 9 1001 09 A 1010 10 B 1011 11 C 1100 12 D 1101 13 E 1110 14 F 1111 15

H-4

Because 16 is a multiple of 2, hexadecimal is a convenient shorthand for representation of 4 binary digits or bits. The rules on arithmetic also hold. Binary Hex 0100 1111 4F + 0110 0010 + 62 1011 0001 B1 To take advantage of this shorthand, all addresses in this manual are shown in hexadecimal notation. It should be noted that the reader should learn to operate i Hex as soon as possible. Continual translation back to decimal is both time consuming and error prone. Working in Hex and binary will quickly force learning of hexadecimal manipulation and the famil- iarity with working with this convenient representation. Although many microcomputer applications can successfully be accom- plished with binary operations, some applications are best performed in decimal. Although the use of 1 decimal character per byte would be a legitimate way to solve this problem, this is am inefficient use of the cap- ability of the 8-bit byte. The microprocessor allows the use of packed BCD representation. This representation is, in 4-bit form: 0 = 0000 1 = 0001 2 = 0010 3 = 0011 4 = 0100 5 = 0101 6 = 0110 7 = 0111 8 = 1000 9 = 1001 In BCD, the number 79 is represented: Binary BCD Hex 01111001 = 79 = 79

H-5

The microprocessor automatically takes this into account and corrects for the fact that Decimal BCD Hex 79 = 01111001 79 = 01111001 +12 = 00010010 12 = 00010010 91 = 10010001 88 = 10001011 The only difference between Hex and BCD representation is that the microprocessor automatically adjusts for the fact that BCD does not allow for Hex values A - F during add and subtract operations. The offset which follows a branch instruction is in signed two's complement form which means that $+50 = +80 = 01010000 and $-50 = -80 = 10110000 Proof = 00000000 The sign for this operation is in bit 7 where an 0 equals positive and a 1 equals negative. This bit is correct for the two9s complement representation but also flags the microprocessor whether to carry or borrow from the address high byte. The following 4 examples represent the combinations of offsets which might occur (all notations are in hexadecimal): Example H.4.l: Forward reference, no page crossing 0105 BNE 0106 +55 0107 Next OP CODE To calculate next instruction if the branch is taken Offset +55 01010101 Address Low for next OP CODE 07 00000111 5C 01011100 with no carry, giving 015C as the result.

H-6

Example H.4.2: Backward reference, no page crossing 015A BNE 015B -55 015C Next OP CODE To calculate if branch is taken, Offset -55 = AB = 10101011 + Address Low for Next OP CODE +5C = 5C = 01011100 07 07 00000111 The carry is expected because of the negative offset and is ignored, thus giving 0107 as the result. Example H.4.3: Backward reference if page boundary crossed 0105 BNE 0106 -55 0107 Next OP CODE To calculate if branch is taken, first calculate a low byte Offset -55 = AB = 10101011 Address Low for Next OP CODE 07 = 07 = 00000111 B2 = B2 = 10110010 There is no carry from a negative offset; therefore, a carry must be made: -1 = -1 = FF = 11111111 + Address High = 01 = D1 = 00000001 00 00 00000000 This gives 00 B2 as a result. Example H.4.4: Forward reference across page boundary 00B0 BNE 00B1 +55 00B2 Next OP CODE To calculate next instruction if branch is taken,

H-7

Offset 55 = 01010101 Address Low for Next OP CODE B2 = 10110010 07 00000111 with carry on positive number. +1 1 = 00000001 Address High 00 = 00000000 1 = 00000001 which gives 0107.

H-8